Norman Jouppi

Norman P. Jouppi is a Fellow and director of the Advanced Architecture Lab at HP Labs. He is well known for his innovations in computer memory systems, including stream prefetch buffers, victim caching, multi-level exclusive caching, and development of the CACTI tool for modeling cache timing, area, and power.

His research innovations have been adopted in microprocessors from most high-performance microprocessor vendors.

He has also been the principal architect and lead designer of several microprocessors, contributed to the architecture and design of graphics accelerators, and extensively researched video, audio, and physical telepresence.

His most recent work includes low-latency high-bandwidth networking for cluster computing, heterogeneous chip multiprocessor architectures, and blade system architectures.

Jouppi joined HP in 2002 from Compaq Computer Corp., where he was a Staff Fellow at Compaq's Western Research Laboratory (WRL) in Palo Alto, California .

From 1984 through 1996 he was also a consulting assistant/associate Professor in the department of Electrical Engineering at Stanford University where he taught classes in VLSI, circuits, and computer architecture.

Jouppi received his PhD in Electrical Engineering from Stanford University in 1984, and a M.S.E.E. from Northwestern University in 1980. While at Stanford he was one of the principal architects and designers of the MIPS microprocessor, as well as a developer of techniques for CMOS VLSI timing verification.

He is currently serving as Chair of ACM SIGARCH , Vice-Chair for Operations of the ACM SIG Governing Board Executive Committee, and on the ACM Council. He is on the editorial board for IEEE Computer Architecture Letters, and holds more than 30 U.S. patents, including one designated a Compaq Key Patent.

He has published over 100 technical papers, with several best paper awards and one ISCA Influential Paper Award. He is a Fellow of the IEEE and of the ACM.