[Gc] [patch] atomic_ops add ppc64 missing bits

Andreas Tobler toa at pop.agri.ch
Sat Jan 27 13:36:55 PST 2007


Hello,

I do not know if this is the right place. But here it comes, while 
hacking on ppc64 I found the attached pieces missing.

With the attached patch the 'make check' passes. There are a lot of ops 
which are not supported. But before the patch, the test failed in one place.

Ok?

Do we need a CL entry? And if so, where ?

Thanks,
Andreas

-------------- next part --------------
Index: src/atomic_ops.h
===================================================================
RCS file: /cvsroot/bdwgc/bdwgc/libatomic_ops-1.2/src/atomic_ops.h,v
retrieving revision 1.1
diff -u -r1.1 atomic_ops.h
--- src/atomic_ops.h	11 Jul 2006 23:29:29 -0000	1.1
+++ src/atomic_ops.h	18 Jan 2007 21:09:18 -0000
@@ -210,7 +210,8 @@
 # if defined(__m68k__)
 #   include "atomic_ops/sysdeps/gcc/m68k.h"
 # endif /* __m68k__ */
-# if defined(__powerpc__) || defined(__ppc__) || defined(__PPC__)
+# if defined(__powerpc__) || defined(__ppc__) || defined(__PPC__) \
+     || defined(__powerpc64__) || defined(__ppc64__)
 #   include "atomic_ops/sysdeps/gcc/powerpc.h"
 # endif /* __powerpc__ */
 # if defined(__arm__) && !defined(AO_USE_PTHREAD_DEFS)
Index: src/atomic_ops/sysdeps/gcc/powerpc.h
===================================================================
RCS file: /cvsroot/bdwgc/bdwgc/libatomic_ops-1.2/src/atomic_ops/sysdeps/gcc/powerpc.h,v
retrieving revision 1.2
diff -u -r1.2 powerpc.h
--- src/atomic_ops/sysdeps/gcc/powerpc.h	14 Dec 2006 21:40:10 -0000	1.2
+++ src/atomic_ops/sysdeps/gcc/powerpc.h	18 Jan 2007 21:09:19 -0000
@@ -62,7 +62,28 @@
 /* with an ordinary load followed by a lwsync.  But the general wisdom	*/
 /* seems to be that a data dependent branch followed by an isync is 	*/
 /* cheaper.  And the documentation is fairly explicit that this also 	*/
-/* has acquire semantics.						*/
+/* has acquire semantics.				                */
+#if defined(__powerpc64__) || defined(__ppc64__) || defined(__64BIT__)
+AO_INLINE AO_t
+AO_load_acquire(volatile AO_t *addr)
+{
+  AO_t result;
+
+  /* FIXME: We should get gcc to allocate one of the condition	*/
+  /* registers.  I always got "impossible constraint" when I	*/
+  /* tried the "y" constraint.					*/
+  __asm__ __volatile__ (
+    "ld %0,%1\n"
+    "cmpd cr7,%0,%0\n"
+    "bne- cr7,1f\n"
+    "1: isync\n"
+    : "=r" (result)
+    : "m"(*addr) : "memory", "cc");
+  return result;
+}
+
+#else
+
 AO_INLINE AO_t
 AO_load_acquire(volatile AO_t *addr)
 {
@@ -81,6 +102,8 @@
   return result;
 }
 
+#endif
+
 #define AO_HAVE_load_acquire
 
 /* We explicitly specify store_release, since it relies 	*/


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