[Gc] [PATCH 2/2]: Hexagon atomic ops

Linas Vepstas linasvepstas at gmail.com
Fri Oct 7 12:19:40 PDT 2011


Implement a handful of basic atomic primatives for the hexagon.

Signed-off-by: Linas Vepstas <linasvepstas at gmail.com>

---
 libatomic_ops/src/atomic_ops.h                     |    3
 libatomic_ops/src/atomic_ops/sysdeps/Makefile.am   |    2
 libatomic_ops/src/atomic_ops/sysdeps/gcc/hexagon.h |  108 +++++++++++++++++++++
 3 files changed, 112 insertions(+), 1 deletion(-)

Index: gc-7.2alpha6/libatomic_ops/src/atomic_ops.h
===================================================================
--- gc-7.2alpha6.orig/libatomic_ops/src/atomic_ops.h	2011-10-07
11:18:39.000000000 -0500
+++ gc-7.2alpha6/libatomic_ops/src/atomic_ops.h	2011-10-07
11:21:59.000000000 -0500
@@ -262,6 +262,9 @@
 # if defined(__avr32__)
 #   include "atomic_ops/sysdeps/gcc/avr32.h"
 # endif
+# if defined(__hexagon__)
+#   include "atomic_ops/sysdeps/gcc/hexagon.h"
+# endif /* __mips__ */
 #endif /* __GNUC__ && !AO_USE_PTHREAD_DEFS */

 #if (defined(__IBMC__) || defined(__IBMCPP__)) && !defined(__GNUC__) \
Index: gc-7.2alpha6/libatomic_ops/src/atomic_ops/sysdeps/Makefile.am
===================================================================
--- gc-7.2alpha6.orig/libatomic_ops/src/atomic_ops/sysdeps/Makefile.am	2011-10-07
11:18:39.000000000 -0500
+++ gc-7.2alpha6/libatomic_ops/src/atomic_ops/sysdeps/Makefile.am	2011-10-07
11:21:59.000000000 -0500
@@ -27,7 +27,7 @@ nobase_sysdep_HEADERS= generic_pthread.h
 	  armcc/arm_v6.h \
 	\
 	  gcc/alpha.h gcc/arm.h gcc/avr32.h gcc/cris.h \
-	  gcc/hppa.h gcc/ia64.h gcc/m68k.h \
+	  gcc/hexagon.h gcc/hppa.h gcc/ia64.h gcc/m68k.h \
 	  gcc/mips.h gcc/powerpc.h gcc/s390.h \
 	  gcc/sh.h gcc/sparc.h gcc/x86.h gcc/x86_64.h \
 	\
Index: gc-7.2alpha6/libatomic_ops/src/atomic_ops/sysdeps/gcc/hexagon.h
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ gc-7.2alpha6/libatomic_ops/src/atomic_ops/sysdeps/gcc/hexagon.h	2011-10-07
13:58:08.000000000 -0500
@@ -0,0 +1,108 @@
+/*
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the
"Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#include "../all_aligned_atomic_load_store.h"
+
+#include "../test_and_set_t_is_ao_t.h"
+
+/* There's also "isync" and "barrier"; however, for all current CPU
+ * versions, "syncht" should suffice.  Likewise, it seems that the
+ * auto-defined versions of *_acquire, *_release or *_full suffice for
+ * all current ISA implementations.
+ */
+AO_INLINE void
+AO_nop_full(void)
+{
+  __asm__ __volatile__("syncht" : : : "memory");
+}
+#define AO_HAVE_nop_full
+
+/* The Hexagon has load-locked, store-conditional primitives, and so
+ * resulting code is very nearly identical to that of powerpc.
+ */
+
+AO_INLINE AO_TS_VAL_t
+AO_test_and_set(volatile AO_TS_t *addr)
+{
+  int oldval;
+  int temp = 1; /* locked value */
+
+  __asm__ __volatile__(
+     "1:\n"
+     "  %0 = memw_locked(%2);\n"        /* load and reserve            */
+     "  {\n"
+     "    p2 = cmp.eq(%0,#0);\n"        /* if load is not zero         */
+     "    if (!p2.new) jump:nt 2f; \n"  /*   we are done               */
+     "  }\n"
+     "  memw_locked(%2,p1) = %3;\n"     /* else store conditional      */
+     "  if (!p1) jump 1b;\n"            /* retry if lost reservation   */
+     "2:\n"                             /* oldval is zero if we set    */
+     : "=&r"(oldval), "+m"(*addr)
+     : "r"(addr), "r"(temp)
+     : "memory", "p1", "p2");
+  return (AO_TS_VAL_t)oldval;
+}
+#define AO_HAVE_test_and_set
+
+
+AO_INLINE int
+AO_compare_and_swap(volatile AO_t *addr, AO_t old, AO_t new_val)
+{
+  AO_t __oldval;
+  int result = 0;
+  __asm__ __volatile__(
+     "1:\n"
+     "  %0 = memw_locked(%3);\n"        /* load and reserve            */
+     "  {\n"
+     "    p2 = cmp.eq(%0,%4);\n"        /* if load is not equal to     */
+     "    if (!p2.new) jump:nt 2f; \n"  /*   old, fail                 */
+     "  }\n"
+     "  memw_locked(%3,p1) = %5;\n"     /* else store conditional      */
+     "  if (!p1) jump 1b;\n"            /* retry if lost reservation   */
+     "  %1 = #1\n"                      /* success, result = 1         */
+     "2:\n"
+     : "=&r" (__oldval), "+r" (result), "+m"(*addr)
+     : "r" (addr), "r" (old), "r" (new_val)
+     : "p1", "p2", "memory"
+  );
+  return result;
+}
+
+#define AO_HAVE_compare_and_swap
+
+
+AO_INLINE AO_t
+AO_fetch_and_add(volatile AO_t *addr, AO_t incr) {
+  AO_t oldval;
+  AO_t newval;
+  __asm__ __volatile__(
+     "1:\n"
+     "  %0 = memw_locked(%3);\n"        /* load and reserve            */
+     "  %1 = add (%0,%4);\n"            /* increment                   */
+     "  memw_locked(%3,p1) = %1;\n"     /* store conditional           */
+     "  if (!p1) jump 1b;\n"            /* retry if lost reservation   */
+     : "=&r"(oldval), "=&r"(newval), "+m"(*addr)
+     : "r"(addr), "r"(incr)
+     : "memory", "p1");
+  return oldval;
+}
+#define AO_HAVE_fetch_and_add
+
+#include "../ao_t_is_int.h"
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