CMOS Programmable Delay Vernier
In the HP 9493 LSI test system, CMOS delay verniers replace the usual bipolar technology and are integrated with digital circuitry to produce a high-performance timing generator in a single monolithic CMOS VLSI formatter chip. This solution achieves bipolar-equivalent resolution, skew, and jitter performance with signi ficantly lower power, cost, and circuit board space.
by Masaharu Goto, James O. Barnes, and Ronnie E. Owens
Article 9 - oct94a9.pdf
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