At one time electronic design engineers only had to contend with designing analog circuits into their products. The only digital-like component in these products was the on/off switch. When digital circuits did come along, their initial use was limited to computation applications. Eventually, engineers realized that digital circuits could be used to implement many of the functions traditionally done in analog circuits. The result of this analog-to-digital migration is that we now have mixed-signal electronic products such as CD players, stereo players, and automotive electronics, which are designed with both analog and digital components.
The primary test instrument of choice for engineers designing mixed-signal systems is the oscilloscope. However, because oscilloscopes have a limited number of input channels, they are not adequate for testing digital systems. Logic analyzers, which allow viewing several digital signals simultaneously, are used for testing digital circuits. While HP is a leader in providing hybrid instruments that combine oscilloscope and logic analyzer technologies for testing mixed-signal systems, as pointed out in Article1, these products are designed with full-featured logic analysis as their goal and the oscilloscope capability is treated as an adjunct to the analyzer. This article introduces six articles on a new family of oscilloscopes and logic analyzers that are targeted for mixed-signal testing, but with the opposite emphasis. These instruments were designed with oscilloscope capabilities as a priority and logic analysis as an adjunct.
Article 2 discusses an application in which the HP 54645D mixed-signal oscilloscope is used to simplify testing and debugging a microcontroller-based mixed-signal design. Topics covered in the other mixed-signal articles in this issue include the concurrent design and features of the HP 54645D mixed-signal oscilloscope and the HP 54645A two-channel oscilloscope (Article 3), the effect of memory depth and peak detection on a digital oscilloscope’s sample rate (Article 4), the use of acquisition clock dithering in the HP 54546A/D to reduce aliasing and improve the display of signals that are subharmonics of the sample clock (Article 5), the oscilloscope-like features of the HP 54620 logic timing analyzer ( Article 6), and the capabilities of the high-speed multiprocessor-based HP 54615B and HP 54616B oscilloscopes (Article 7).
Monitoring yeast growth in fermentation (a process associated with making beer) is one of the applica-tions for the HP E5050A colloid dielectric probe (Article 8). The HP 5050A probe, in conjunction with an HP 4285A precision LCR meter and an HP Vectra personal computer, provides online monitoring of colloidal liquid materials (e.g. water-in-oil or oil-in-water emulsions) in the food, chemical, and pharmaceutical industries. Key parameters of colloids are often directly related to or can be derived from the permittivity or conductivity of the material. The sensing technique used in the HP E5050A provides permittivity versus frequency characteristics, which can be used to determine the concentration, size, structure, and consistency of colloidal dispersions.
The need for reliable networks has brought about a proliferation of test equipment for monitoring the health of a network. The next two articles describe network-related test products from HP’s Communications Test Division. The first product is the HP E4219 ATM network impairment emulator (Article 9). This emulator allows telecommunication equipment service providers to emulate ATM (Asynchronous Transfer Mode) networks before deploying their equipment or services. The second article describes the HP E4214A Broadband ISDN UNI signaling test software (Article 10). UNI (user-network interface) is the boundary between a private or public network and the user equipment. By providing protocol message decoding and encoding, the E4214A software allows engineers to develop, troubleshoot, and verify the features and functionality of UNI signaling.
Once the equipment is in place to capture information about activity on the network, the next thing we need is some software that allows us to monitor and control network activity from a central console. The SNMP++ and SNMPGen software development tools (Article 11) allow developers to create object-oriented network management applications quickly without having to be experts on network protocols.
SNMP++ is a set of C++ classes that provide an object-oriented application programming interface to the services of the Simple Network Management Protocol (SNMP). SNMPGen uses SNMP++ to generate C++ code automatically.
Many of the circuits used in network equipment and network test instruments contain microwave com-ponents. A network analyzer is used to test these components. A network analyzer measures the magnitude and phase of the reflection and transmission characteristics of a microwave component as a function of frequency. This information is needed by designers so that they can verify that their components will work when they are inserted into a microwave system (e.g., cellular phones, broadcast and cable TV, long-distance telephone transmission, satellite communications, airplane radar, and so on). Since the introduction of the early models of the family of HP network analyzers known as the HP 8720 family, more and more of these instruments are being used in production test systems as opposed to their previous R&D role. This change has created a need for more measurement speed and an expanded I/O capability for integration into production test systems. Article 12 describes the HP 8720D network analyzer, which contains features specifically targeted for the production environment.
HP’s Design Technology Conference (DTC) is an internal conference that enables HP engineers to share ideas, best practices, and results among HP people involved in the development and application of integrated circuit design technologies. When appropriate, we are able to publish some of the papers from this conference in the HP Journal. The last five articles in this issue are from the 1996 DTC conference. The first article (Article 13) describes a project to estimate the impact of interconnect parameters on the performance of high-end processors (interconnect is the electrical conducting paths between devices or blocks on ICs). The objective was to use this information to optimize interconnect geometry.
The next two DTC articles deal with mixed-signal modeling. In the first article (Article 14), the design of a phase-locked loop, which is used in several HP ASICs, involved transferring the digital portion of the circuit to a behavioral VHDL model and creating a special behavioral model for the analog portion. This separation enabled ASIC designers to run system simulations. The second article of this genre (Article 15) describes using a tool called SABER MAST for mixed-mode behavioral modeling. The tool provides a speedup of two orders of magnitude over traditional analog-oriented SPICE simulations.
A combination of commercial ASIC vendor-supplied tools and some internally developed tools were part of a physical design methodology that enabled designers to develop 1.1-million-raw-basic-cell, 0.35-mm gate arrays for HP Exemplar S-class and X-class technical servers (Article 16).
Finally, the ability to quickly turn around a custom IC design is very important in the IC design business. Article 17 describes how with the proper mix of new tools and methodologies, a 1.7-million-FET image processing chip was designed and verified in eight months.