In December 1993, a very unusual meeting took place.
Top-level scientists, engineers, and executives from both Intel and Hewlett-Packard met in the basement of building 3 at Hewlett-Packard's Palo Alto site, just downstairs from the offices of Bill Hewlett and Dave Packard. At this meeting Hewlett Packard presented details of HP Labs' PA-WW (PA-WideWord) architecture research begun in 1990, and the conclusions of the extensive HP product group analysis that had established the superior performance potential of EPIC architecture. As a result of this meeting, joint Intel/HP technical and business evaluation teams were chartered.
Early in 1994, the technical evaluation teams from Intel and Hewlett-Packard met in a closed meeting room at an HP training site. Two filing cabinets sat locked near the table. Inside one cabinet lay HP's 'gold book', a slim volume containing the specifications of HP Labs' PA-WW processor architecture. Inside the other were documents from Intel's own 64-bit architecture development. The two groups shared documents, compared notes and discussed future plans.
At the end of the technical meetings, the representatives from each company had a fair idea of what the other company was planning. Both sides had already agreed that the current architectures of the day (RISC and CISC) would inevitably hit a dead end. The concurrent business team discussions continued well beyond the conclusion of the technical meetings, and led to a partnership agreement. And so it was that Intel and HP decided to join forces to usher in a new era in computer architecture.
These historic meetings led to the inception of the IA-64 program, now the Itanium™ processor family architecture. It had happened because the directors of the PA-Wide Word project saw the astounding promise of this new architecture, and knew that to bring it to its fullest potential, HP would need a strategic partner.
Bill Worley was the technical director of the project.
He explains: "In July 1992, I made a presentation to the HP executive committee at the annual HP Labs executive review. I told them that I thought that PA-WW was a new genre of architecture and that we really ought to try to make it an industry standard. I explained that we probably couldn't do that by ourselves, should try to find a partner, and that I thought that a semiconductor manufacturing partner would be ideal. Of course, Intel was the premier candidate."
Dick Lampman (now Director of HP Labs) and Bill had been chartered in January 1990 by Frank Carrubba (then Director of HP Labs) to begin this research work in January 1990. Dick and Bill agreed that Dick would act as administrative and managerial director of the program, and that Bill would act as technical director.
Bill and his inventive team began work that January, drawing upon even earlier HP Labs work begun by Bob Rau and his team in 1998, on the next generation of architecture that would one day replace PA-RISC. A relaxed, multi-disciplinary approach allowed the team to pursue some intriguing new approaches, melding some of the newest techniques while drawing extensively from experiences of past architectures.
Bill explains how the team worked: "Dick and I set out to form a working group that was not an organizational entity; it just drew members from each the groups of HP Labs that were working in related areas, and comprised the de-facto core team of the program."
As the work progressed, Rick Amerson accepted the role of engineering manager, and Gene Emerson assumed the role of VLSI design manager. Somewhat later, Rajiv Gupta became the architecture manager. Bob Rau's and Josh Fisher's groups were active participants throughout the effort. Over the course of the program, the team also was joined by representatives of HP product and technology groups, expert outside consultants, and, for an extended period, by a collaborative research team from Hitachi Ltd., led by Dr. Yasuyuki Okada.
The group tackled the difficult issues of the demands that future applications would place on a new architecture, and how best to achieve the high levels of instruction-level parallelism (ILP) that would allow future systems to continue to achieve ever growing levels of performance.
"We were very mindful that we were trying to take the next step in computer architecture. We had realized ever since the development of PA-RISC that the next quantum step in architecture would require high levels of ILP. We knew that if we were successful, we could one day establish a new bar and surpass the CISC and out-of-order superscalar RISC architectures."
"We knew a lot about scientific computing, and we really beefed up the floating point capabilities. Some of our early prototype compilers were achieving demonstrably optimal codes for the Livermore loop benchmarks."
"We included multimedia instructions equivalent to those in PA-RISC, but not nearly to the extent of the final Itanium™ multimedia instructions. The final instruction repertoire drew both from the MMX work that Intel had done, as well as from PA-RISC. In fact, if one looks closely, the Itanium™ multimedia instruction repertoire essentially is a union of the HP ideas had and the Intel ideas. There was little tradeoff."
Bill and his team also realized the need for significantly enhanced encryption capabilities. System security and data privacy are central concerns for e-commerce, both for Internet companies and for individuals. Strong cryptographic techniques will be of growing importance, and the cryptographic codes must be extremely fast.
Bill has a profound understanding of the potential of the IPF architecture as it matures and comes into its own. As was the case with RISC architectures, it will take time to for the IPF compilers and micro architectures to mature and evolve to the point of total superiority, he has no doubt that it will happen.
He explains: "When we introduce McKinley, the first truly outstanding hardware implementation of the Itanium™ architecture, I believe there will be a growing appreciation for what this architecture can do."
Even the early HP Labs research has born futuristic fruit - a good omen. As part of the early PA Wide-Word program, the team designed and built a 1012 logic operations per second simulator to test processor chip designs. Because the group was operating on a tight budget they couldn't afford to pay for perfect parts. They therefore included functionality that permitted detection and avoidance of silicon and packaging defects, then used only the remaining correct areas of the chips and packages.
Bill recalls: "Rick Amerson and his team did this purely as an economic necessity, but it turned out that the ability to design redundantly and map out areas not being used looks like it may be important for quantum computing. A number of papers and prizes have been awarded for results that stemmed from this work.
"I find this truly delightful ... A design for a fast simulator of a new computer micro architectures led to applications and directions we could never have foreseen at the time."
by Joan Tharpe