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A novel way to better chips

New design could lead to chips that cost less, consume less power, but provide higher performance
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The implication is that we can likely figure out how to make Moore's Law go on for several decades.

By Jamie Beckett, January 2007

Researchers at HP Labs have demonstrated a new chip architecture that could lead to dramatic increases in performance without some of the problems in current designs.

For decades, increases in chip performance have come about largely by shrinking transistors and wires to pack more power into a smaller space. But transistors can only get so small before problems of heat generation, defects and basic physics get in the way.

The researchers' method could allow chips to be built with transistors that are the same size as in today's devices. Their design combines a nanoscale crossbar switch structure with conventional CMOS to create a hybrid chip with higher density while requiring less power and generating less heat.

Moore's law extended?


"The implication is that we can likely figure out how to make Moore's Law -- which is to continually increase the capacity of chips -- go on for several decades rather than running out in the next decade as many expect," said Stan Williams, an HP Senior Fellow who has been leading HP Labs' Quantum Science Research group for more than 10 years.

The researchers, Greg Snider and Williams, unveiled their work in a paper that will be featured in the Jan. 24 issue of Nanotechnology, a publication of the British Institute of Physics. The research was conducted using classic modeling and simulation techniques, but engineers are now at work producing an actual chip that could eventually be fabricated in a standard facility.

The scientists have applied to their approach to field-programmable gate arrays (FPGAs) -- integrated circuits that can be adapted by end users for specific applications in a way that could use less energy, provide up to eight times the density and cost less than existing FPGAs.

They believe a similar concept for placing switches in the interconnect wiring could be applied to other types of integrated circuits.

Shrinking wires, not transistors

The researchers say they can avoid shrinking transistors by removing the wiring and switches between the logic cells on the silicon layer of the FPGA, leaving more room for logic gates and allowing them to be placed closer together. The wiring and switches are replaced by a nanowire interconnect that performs the same functions but resides in a layer above the transistors.

"This way, the transistors are large enough that they stay very reliable," Williams says. "You gain better performance by shrinking the wires instead. These connective nanowires and switches may even be massively defective and the circuit will still work."

FPGAs provide a particularly useful demonstration vehicle because most of the silicon used some 80 percent -- is dedicated to wires and switches and only about 20 percent is dedicated to logic.

Prototype in progress

If successful, the new architecture, dubbed field programmable nanowire interconnect (FPNI), could change the balance in the chip industry with the use of more FPGAs. Because FPGAs are reconfigurable, they can be repaired or improved even after they're inside a product.

But they're also quite expensive, so businesses commonly use them during the product-development phase and later switch to Application Specific Integrated Circuits (ASICs). That could change if less-expensive FPGAs were available.

Williams says that his team is working with engineers in the Technology Development Organization of HP's Imaging and Printing Group to build a working prototype chip in an HP fabrication facility in Corvallis, Oregon, later this year.

Defect-tolerant architecture


This is the same facility that fabricated the FPGA chips used in the HP Labs Teramac project in the early 1990s, for which Greg Snider was the chief architect.

Teramac, a million-gate computer that functioned perfectly despite its 220,000 defective parts, was an early demonstration of the defect-tolerant architecture that Williams' lab has explored since then. The architecture means that researchers can make computing devices using nanowires, which are defect-prone because of their size.

The move from research to development is a first for Williams' lab, which has been at the leading edge of nanoelectronic research.

That presents a significant challenge. "Just because we make certain things work in the lab doesn't mean you can make a robust chip out of it," Williams says. "Now the real work begins."

Not that he's sorry about it. "This is a major milestone for us," he adds. "Our goal is to have something by 2010 that we can give customers to try."


Related links

» HP presents alternate strategy for chip improvement
» Quantum Science Research group
» Nano/CMOS architectures using a field-programmable nanowire interconnect

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