Paper on Defect-Tolerant Computer Architecture Makes News
June 16, 1998
A paper published in the June 12 issue of Science on a defect-tolerant computer architecture and its implications for nanotechnology is making news. The paper -- written by HP Labs researchers Phil Kuekes, Greg Snider, and Stan Williams along with UCLA chemist James Heath -- discusses the Teramac massively parallel experimental computer built at HP Labs in Palo Alto. Although the Teramac computer has 220,000 hardware defects, it has performed some tasks 100 times faster than a single-processor high-end workstation. The key is the Teramac's defect-tolerant architecture, which uses high communications bandwidth to route around the defects.
Reporters from the Los Angeles Times, MSNBC, Reuters, Associated Press, the BBC World Service, Der Spiegel, and other media have interviewed the co-authors on their findings.
The media's interest likely stems from the paper's implications for nanotechnology. As the authors put it in their paper, "It may be feasible to chemically synthesize individual electronic components with less than a 100% yield, assemble them into systems with appreciable uncertainty in their connectivity, and still create a powerful and reliable data communications network."
The MSNBC article says, "Such a 'defect-tolerant' architecture could bridge the gap between the current generation of microchips and the next generation of molecular-scale computers."
Kuekes and Snider work in the Computer Systems Lab at HP Labs; Stan Williams manages the Quantum Structures Research Initiative at HP Labs, which is investigating molecular-sized electronic devices.
An in-depth interview
with Stan is available on HP Labs' external website.
The Science News Service has posted an
article about the paper. Subscribers to Science Online
can read the
paper itself (it's about half way down the page). Wired News
has posted a