Jianhua (Joshua) Yang

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Senior Researcher
Palo Alto

Biography

R&D Engineer
Huawei Technologies
2000 - 2001

Education:
University of Wisconsin - Madison
Ph. D , Materials Science Program
Thesis: Engineering and Characterizing Nanoscale Multilayers for Magnetic Tunnel Junctions

University of Wisconsin - Madison
Matster, Materials Science Program

Southeast University, Nanjing, China
B.S. , Materials processing Engineering

Authored and co-authored about 60 papers in academic journals, over 50 papers in international technical conferences and holding 6 granted and over 60 pending US Patents.

 

Research interests

Nanoelectronics, Nanoionics, Nanothermodynamics especailly for non-volatile memory technologies: fabrications, characterizations and applications.

Awards

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Publications

Selected recent papers:

Patents

6

Professional activities

Co-Editor:
Applied Phyisc A This is a Non-HP site


Book/Journal issue (Ed.):

  1. 'Non-volatile memory based on  nanostructures This is a Non-HP site', 2011, NANOTECHNOLOGY This is a Non-HP site
  2. 'Special Issue on memristive and resistive devices and systems This is a Non-HP site', 2011, APPLIED PHYSICS A This is a Non-HP site  

Book chapter:
'Oxide based memristive nanodevices' in book 'Emerging Nonvolatile Memories', in press

Symposium Chair:

IEEE Nanotechnology 8th Annual Symposium on 'Emerging Non-Volatile Memory Technologies This is a Non-HP site', 2012, Santa Clara, CA, USA

Program/technical committees:

  1. Executive Member, IEEE Nanotechnology Council ( This is a Non-HP siteSF & Bayarea)
  2. The International Conference on Advances in Circuits, Electronics and Micro-electronics (CENICS);
  3. 11th Non-Volatile Memory Technology Symposium This is a Non-HP site (NVMTS 2011)


Recent invited talks:

  1. International Conference on Communications, Circuits and Systems (ICCCAS 2009) San Jose, California.
  2. Seminar, 2009, University of California, Santa Cruz, California.
  3. The 7th International Conference on Advanced Materials and Devices (ICAMD 2009), Jeju island, Korea.
  4. Seminar, 2009, Seoul National University, Korea.
  5. Invited Lecture, May/2009, UCSC-NASA Ames Research Center,California.
  6. The 10th Non-volatile memory technology symposium (NVMTS 2009), Portland, Oregon.
  7. International Symposium on Integrated Functionalities ( ISIF 2010), San Juan, Puerto Rico.
  8. Advances in nonvolatile memory materials and devices (2010), Suzhou, China.
  9. Seminar, 2010, Peking University, Beijing, China.
  10. Seminar, 2010, Chinese Academy of Science, Beijing, China.
  11. International Symposium on Materials for Enabling Nanodevices (ISMEN 2010), UCLA, California.
  12. seminar, 2011, IEEE Computer Society, San Jose California.
  13. The Frontier of Functional-Oxide Nano Electronics workshop, 2011, Tsukuba, Japan.
  14. Seminar, 2011, IEEE Electronic Device Society, Santa Clara, California.
  15. The 11th Non-volatile memory technology symposium (NVMTS 2011), Shanghai, China (Keynote).