Matteo Monchiero

Researcher
Exascale Computing Lab
Palo Alto

Biography

Matteo Monchiero has been with HP Labs -- Palo Alto since April 2007 working in the Exascale Computing Lab. He received his undergraduate degree (Laurea) and PhD from Politecnico di Milano in 2003 and 2007 respectively. Since October 2005 to June 2006, he was a doctoral visiting student at the Universitat Politecnica de Catalunya (UPC), Barcelona, working with Prof. Antonio Gonzalez and Prof. Ramon Canal. His past research has been around VLSI design, System-on-Chip design, Branch Prediction, FPGAs, power and thermal aware architectures, and processor simulation.

 

Research interests

My research interests are in simulation and architecture of scalable multicore and multiprocessor systems and more recently datacenter system architecture.

Publications

Scalable Architectures and Simulation

  • Eduardo Argollo, Ayose Falcon, Paolo Faraboschi, Matteo Monchiero, and Daniel Ortega. COTSon: Infrastructure for full system simulation. In ACM SIGOPS Operating System Reviews. January 2009
  • Matteo Monchiero, Jung Ho Ahn, Ayose Falcon, Daniel Ortega, and Paolo Faraboschi. How to Simulate 1,000 cores. In dasCMP'08: Workshop on Design, Architecture, and Simulation of Chip Multi-Processors, held in conjunction with MICRO-41. November 9, 2008, Lake Como, Italy
  • Dana Vantrease, Robert Schreiber, Matteo Monchiero, Moray McLaren, Norman P. Jouppi, Marco Fiorentino, Al Davis, Nathan Binkert, Raymond G. Beausoleil, and Jung Ho Ahn. Corona: System Implications of Emerging Nanophotonic Technology. In ISCA'08: Proceedings of the 34th annual international symposium on Computer architecture. Beijing, China. June 21-25, 2008
Power and Thermal Aware Architectures
  • Shyamkumar Thoziyoor, Jung Ho Ahn, Matteo Monchiero, Jay B. Brockman, and Norman P. Jouppi. A Comprehensive Memory Modeling Tool and its Application to the Design and Analysis of Future Memory Hierarchies. In ISCA'08: Proceedings of the 34th annual international symposium on Computer architecture. Beijing, China. June 21-25, 2008
  • Matteo Monchiero, Ramon Canal, and Antonio Gonzalez. Power/Performance/Thermal Design Space Exploration for Multicore Architectures. IEEE Transactions on Parallel and Distributed Systems. 19(5):666-681, May 2008
  • Matteo Monchiero, Ramon Canal, and Antonio Gonzalez. Design Space Exploration for Multicore Architectures: A Power/ Performance/ Thermal View. In Proceedings of ACM ICS'06  International Conference on Supercomputing, Cairns, Australia. June 2830, 2006
Network-on-Chip-based Multiprocessors
  • Gianluca Palermo, Oreste Villa, Matteo Monchiero and Cristina Silvano. A Modular Approach to Model Heterogeneous MPSoC at Cycle Level. In DSD 2008: 11th Euromicro Conference on Digital System Design. Parma Italy, September 3-5, 2008
  • Matteo Monchiero, Gianluca Palermo, Cristina Silvano, and Oreste Villa. Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors. Elsevier Journal of System Architecture (JSA)  Special Issue on SAMOS'06,53(10):719-732, October 2007
  • Matteo Monchiero, Gianluca Palermo, Cristina Silvano, and Oreste Villa. Efficient Synchronization for Embedded on-Chip Multiprocessors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 14(10):1049-1062, October 2006
  • Matteo Monchiero, Gianluca Palermo, Cristina Silvano, and Oreste Villa. Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors. In Proceedings of IEEE IC-SAMOS'06: Embedded Computer Systems: Architectures, MOdeling, and Simulation, Samos, Greece. July 17-20, 2006
  • Matteo Monchiero, Gianluca Palermo, Cristina Silvano, and Oreste Villa. Power/Performance Hardware Optimization for Synchronization Intensive Applications in MPSoCs. In Proceedings of IEEE/ACM DATE'06 -- Design, Automation and Test in Europe, Munich, Germany. March 6--10, 2006
  • Matteo Monchiero, Gianluca Palermo, Cristina Silvano, and Oreste Villa. An Efficient Synchronization Technique for Multiprocessor Systems on-Chip. ACM SIGARCH Computer Architecture News, Special Issue: MEDEA'05 (International Workshop on MEmory performance: DEaling with Applications, systems and architecture -- held in conjunction with PACT'05), 34(1):33-40, March 2006
  • Oreste Villa, Patrick Schaumont, Ingrid Verbauwhede, Matteo Monchiero and Gianluca Palermo. Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip. In Proceedings of IEEE/ACM DATE'05 -- Design, Automation and Test in Europe, March 2005
Multiprocessors on FPGA
  • Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi and Donatella Sciuto. Lightweight DMA Management Mechanisms for Multiprocessors on FPGA. In ASAP'08: Proceedings of the 19th IEEE International Conference Application-specific Systems, Architectures and Processors. Leuven, Belgium, July 2-4, 2008
  • Antonino Tumeo, Marco Branca, Lorenzo Camerini, Marco Ceriani, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto. A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications. In Proceedings of IEEE/ACM DATE'08 -- Design, Automation and Test in Europe, Munich, Germany. March 10--14, 2008
  • Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, and Donatella Sciuto. A Self-Reconfigurable Implementation of the JPEG Encoder. In ASAP'07: Proceedings of the 18th International Conference on Application-Specific Systems, Architectures and Processors. Montreal, Canada. July 8-11, 2007
  • Antonino Tumeo, Marco Branca, Lorenzo Camerini, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, and Donatella Sciuto. An Interrupt Controller for FPGA-based Multiprocessors. In Proceedings of IEEE IC-SAMOS'07: Embedded Computer Systems: Architectures, MOdeling, and Simulation, Samos, Greece. July 1619, 2007
  • Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, and Donatella Sciuto. A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs. In Proceedings of IEEE ISVLSI'07-- International Symposium on VLSI. Porto Alegre, Brasil. May 9-11, 2007
  • Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, and Donatella Sciuto. An Internal Partial Dynamic Reconfiguration Implementation of the JPEG Encoder for Low-Cost FPGAs. In Proceedings of IEEE ISVLSI'07-- International Symposium on VLSI. Porto Alegre, Brasil. May 9-11, 2007
  • Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, and Donatella Sciuto. A Design Kit for a Fully Working Shared Memory Multiprocessor on FPGA. In Proceedings of ACM GLSVLSI'07 -- Great Lakes Symposium on VLSI. Stresa, Italy. March 11-13, 2007
  • Simone Borgio, Davide Bosisio, Matteo Monchiero, Antonino Tumeo, Fabrizio Ferrandi, Marco Santambrogio, and Donatella Sciuto. Hardware DWT accelerator for MultiProcessor System On-Chip on FPGA. In Proceedings of IEEE IC-SAMOS'06: Embedded Computer Systems: Architectures, MOdeling, and Simulation, Samos, Greece. July 1720, 2006
Branch Prediction
  • Matteo Monchiero and Gianluca Palermo. The Combined Perceptron Branch Predictor In Proceedings of IEEE/ACM Euro-Par'05 -- Parallel Computer Architecture and ILP Track, Lisbon, Portugal. August 30 -- September 2, 2005
  • Matteo Monchiero, Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria and Roberto Zafalon. Low-Power Branch Prediction Techniques for VLIW Architectures: A Compiler-Hints Based Approach. Integration, The VLSI Journal -- Special Issue on GLSVLSI'04, 38(3):515-524, January 2005
  • Matteo Monchiero, Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria and Roberto Zafalon. Power-Aware Branch Prediction Techniques: A Compiler-Hints Based Approach for VLIW Processors. In Prooceedings of ACM GLSVLSI'04 -- Great Lakes Symposium on VLSI, Boston, MA, April 2004
Miscellanea
  • Guido Bertoni, Vittorio Zaccaria, Luca Breveglieri, Matteo Monchiero, and Gianluca Palermo A Power Attack Methodology to AES Based on Induced Cache Misses: Procedure, Evaluation and Possible Countermeasures. In New Trends in Cryptographic Systems, 2006, Nova Science Publishers
  • D. Barretta, L. Breveglieri, P. Maistri, M. Monchiero, L. Negri, A. Pagni, G. Palermo, M. Sami, C. Silvano, O. Villa and R. Zafalon. Low Power Architectures. In Mobile Information Systems: Infrastructure and Design for Adaptivity and Flexibility, 2006, Springer
  • Guido Bertoni, Vittorio Zaccaria, Luca Breveglieri, Matteo Monchiero and Gianluca Palermo. AES Power Attack Based on Induced Cache Miss and Countermeasure. In Proceedings of IEEE ITCC'05 - Track on Embedded Cryptographic Systems, April 2005
Not refereed posters/abstracts
  • Matteo Monchiero, Ramon Canal and Antonio Gonz�lez. Design Space Exploration for MulticoreArchitectures: A Power/ Performance/ Thermal View. Intel Academic Forum 2006 . Dublin (Ireland), June 2006
  • Matteo Monchiero, Gianluca Palermo, Cristina Silvano, and Oreste Villa. Efficient Synchronization for Embedded on-Chip Multiprocessors. In ACACES'05: First International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems. July 24 to July 30, 2005. L'Aquila, Italy
  • Matteo Monchiero. Fine-grained Thread-Level Parallelism: Toward Interconnect-Centric Computer Architecture. In DATE'05 Ph.D. Forum  Design, Automation and Test in Europe, March 2005
PhD and Master thesis
  • Matteo Monchiero. Power/performance analysis and optimization of multicore architectures. PhD Thesis. Politecnico di Milano. April 2007
  • Matteo Monchiero. Analysis and Design of Power-Aware Branch Prediction Techniques for VLIW Processors. Master Thesis. Politecnico di Milano. October 2003

Professional activities

MICRO-41 Publication co-chair