Paolo Faraboschi

Distinguished Technologist
Exascale Computing Lab
Sant Cugat del Valles

Biography

Paolo is a Distinguished Technologist in the Exascale Computing Lab, Barcelona Research Office. He has been with HP Labs since 1994.

Since 2003, Paolo leads a research group in Barcelona (Spain) focused on system-level simulation and modeling of compute fabrics for next-generation IT.

From 1995 to 2003 he was the technical lead of the Custom-Fit Processors Project at HP Labs Cambridge (MA). In that role, he was the principal architect of the instruction set architecture (ISA) of the Lx/ST200This is a Non-HP site family of VLIW embedded processor cores (developed as a partnership between HP Labs and STMicroelectronics)

Paolo holds a Ph.D (Dottorato) in EECS (1993) and an M.S. (Laurea) in Electrical Engineering (1989) from the University of GenoaThis is a Non-HP site (Italy).

 

Research interests

Paolo's interests skirt the boundaries of hardware and software, including highly-parallel systems, virtualization, simulation, compilers, VLIW architectures.

Publications

See publication pageThis is a Non-HP site for details

Patents

13

Professional activities

Paolo is an active member of the computer architecture community, and regularly serves in program and organization committees. He was recently Program Chair for  MICRO41 (2008)This is a Non-HP site and in the past for MICRO34 (2001)This is a Non-HP site. He also was General Chair for MICRO38, Progam Chair for CASES'03This is a Non-HP site and General Chair for CASES'05This is a Non-HP siteThis is a Non-HP site. He is a co-author (with Josh Fisher and Cliff Young) of the book "Embedded Computing: a VLIW approach to architecture, compilers and tools"This is a Non-HP site. Paolo also serves in the industrial advisory board of the HiPEACThis is a Non-HP site European network of excellence on High Performance and Emedded Architectures and Compilers, and is currently an Associated Editor of ACM TACOThis is a Non-HP site (Transactions on Architecture and Code Optimization)