Sheng Li

Senior Research Scientist
Palo Alto

Biography



Sheng Li is a senior research scientist at HP Labs. His research focuses on computer architecture, VLSI, and parallel computing and OS. He led the development of McPAT, an integrated power, area, and timing modeling framework for manycore architecture that has become a standard infrastructure for architecture research in both industry and academia. Sheng Li received his Ph.D. in Electrical Engineering from the University of Notre Dame in 2010. He has published more than 20 technical papers and has 19 patents, including both awarded and pending.

 

Research interests

  • Computer Architecture: manycore architectures, memory systems, interconnect networks, resilient and energy efficient systems, computer architecture simulation and modeling, SoC architectures, architecture implications of emerging technologies such as 3D stacking integration and non-volatile memory
  • Parallel Computing and OS: parallel architectures and algorithms, power efficient datacenters and supercomputing systems, manycore OS design and implementation with emphasis on parallel computing and virtual memory management
  • VLSI: FPGA/ASIC design and analysis, System/circuit/device characterization and modeling

Awards

  • Hewlett-Packard Recognition, 2013
  • Hewlett-Packard eAward, in appreciation of outstanding efforts for the PERFECT DARPA proposal, 2012
  • Hewlett-Packard eAward, for the contributions to accepted SC and Micro papers and a best-paper nominated ICCAD paper, 2011 
  • IEEE/ACM William J. McCalla ICCAD Best Paper Award Nomination, 2011 
  • HiPEAC Paper Award, 2011 
  • Hewlett-Packard eAward, in appreciation of outstanding efforts for outstanding innovation in modeling of embedded processors, 2010 

Publications

  1. S. Li J. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen, N. P. Jouppi, “The McPAT Framework for Multicore and Manycore Architectures: Simultaneously Modeling Power, Area, and Timing,” The ACM Transactions on Architecture and Code Optimization, Volume 10, Issue 1, April, 2013, Article No. 5
  2. J. H. Ahn, S. Li, S. O, N. Jouppi, “McSimA+: A Manycore Simulator with Application-level+ Simulation and Detailed Microarchitecture Modeling,” in Proceedings of the 14th IEEE International Symposium on Performance Analysis of Systems and Software (Full Paper Acceptance Rate = 23/87 =26%)
  3. S. Li, D. Yoon, K. Chen, J. Zhao, J. Ahn, Y. Xie, J. B. Brockman, N. P. Jouppi, “MAGE: Adaptive Granularity and ECC for Resilient and Power Efficient Memory Systems,” in Proceedings of the 25th ACM/IEEE Conference for High Performance Computing, Networking, Storage and Analysis (SC), 2012. (Acceptance Rate = 100/472= 21%)
  4. S. Li, K. Lim, P. Faraboschi, J. Chang, P. Ranganathan, N. P. Jouppi, “System-Level Integrated Server Architectures for Scale-Out Datacenters,” in Proceedings of the 44th IEEE/ACM International Symposium on Microarchitecture (MICRO), 2011. (Acceptance Rate = 44/209= 21%)
  5. S. Li, K. Chen, M. Hsieh, N. Muralimanohar, C. D. Kersey, J. B. Brockman, A. F. Rodrigues, N. P. Jouppi, “System Implications of Memory Reliability in Exascale Computing,” in Proceedings of the 24th ACM/IEEE Conference for High Performance Computing, Networking, Storage and Analysis (SC), 2011. (Acceptance Rate = 74/352= 21%)
  6. S. Li, K. Chen, J. Ahn, J. B. Brockman, N. P. Jouppi, “CACTI-P: Architecture-Level Modeling for SRAM-based Structures with Advanced Leakage Reduction Techniques,” in Proceedings of the 13rd IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2011. (Acceptance Rate = 106/349= 30%) (IEEE/ACM William J. McCalla ICCAD Best Paper Award Nomination)
  7. K. Chen, S. Li, N. Muralimanohar, J. H. Ahn, J. Brockman, N. Jouppi, “CACTI-3DD: Architecture level Modeling for 3D Die-stacked DRAM Main Memory,” in Proceedings of Design, Automation & Test in Europe (DATE), 2012. (Acceptance Rate = 46/212= 21%) 
  8. S. Li, P. Faraboschi, M. Krause, K. Chen, N. Jouppi, “Memory Network: Scalable Memory Systems for Data-centric Datacenters,” in Proceedings of HP TechCon 2013. (Acceptance Rate = 130/1886 = 7%)
  9. S. Li, K. Lim, P. Faraboschi, J. Chang, N. Jouppi, P. Ranganathan, “SoC Support for Network-Aggregated Hyperscale Servers,” in Proceedings of HP TechCon 2012. (Acceptance Rate = 130/1769= 7%;)
  10. S. Li, K. Lim, P. Faraboschi, J. Chang, N. Jouppi, P. Ranganathan, “A System-Level Integrated Architecture for Scale-Out Computing,” in Proceedings of HP TechCon 2011. (Acceptance Rate =130/1627 = 8%)
  11. S. Li, S. Kuntz, J. B. Brockman, P. M. Kogge, “Lightweight Chip Multi-Threading (LCMT): Maximizing Fine-Grained Parallelism On-Chip,” IEEE Transactions on Parallel and Distributed Systems, volume 22, issue 7, pp. 1178|1191, July, 2011.
  12. S. Li, J. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen, N. P. Jouppi, “An Integrated Power, Area, and Timing Modeling Framework and its Application to Scaling and Clustering Tradeoffs in Future Manycore Architecture,” in Proceedings of the 42nd IEEE/ACM International Symposium on Microarchitecture (MICRO), 2009. (Acceptance Rate = 52/210= 24%, google scholar citation count: 270 as of April 2013 )
  13. J. B. Brockman, S. Li, A. Kashyap, P.M. Kogge, “Design of a Mask-Programmable Memory/Multiplier Array Using G4-FET Technology,” in Proceedings of the 45th ACM/IEEE Design Automation Conference (DAC), 2008. (Acceptance Rate = 147/639 = 23%)
  14. S. Li, S. Kuntz, P. M. Kogge, J. B. Brockman, “Memory Model Effects on Application Performance for a Lightweight Multithreaded Architecture,” in Proceedings of the 22nd IEEE International Parallel and Distributed Processing Symposium (IPDPS), workshop on Multithreaded Architectures and Applications, 2008. 
  15. S. Li, A. Kashyap, S. Kuntz, J. B. Brockman, P. M. Kogge, P. Springer, G. Block, “A Heterogeneous Lightweight Multithreaded Architecture,” in Proceedings of the 21st IEEE International Parallel and Distributed Processing Symposium (IPDPS), workshop on Multithreaded Architectures and Applications, 2007. 
  16. P. Jiang, S. Quan, S. Li, Q. Li, “Control System of High-density Optical Storage,” Journal of Application of Electronic Technique, volume 31, issue 1, 2005.
  17. Y. Li, Q. Li, Y. Guo, S. Li, “Research on Control System of High-density Optical Disc Mastering,” Journal of Optics and Precision Engineering, volume 12, issue 1, 2004.
  18. L. Huang, Y. Guo, P. Jiang, S. Li, Y. Li, Z. Cheng, “Control System for High-precision Turn Table,” Journal of Tsinghua University, volume 44, issue 8, 2004. 
  19. P. Jiang, G. Qi, D. Xu, Q. Li, S. Li, Y. Li, “Design and Research on Control System for High Precision Table,” Journal of Optical Technique, volume 29, issue 6, 2003.
  20. S. Li, Y. Li, Y. Zi, Q. Li, J. Gu, L. Huang, “New Control Scheme in High Density Optical Disk Mastering System,” in Proceedings of the SPIE International Symposium on Advanced Optical Storage Technology, 2002. 
  21. S. Li, K. Chen, J. Brockman, N. Jouppi, “Performance Impacts of Non-blocking Caches in Out-oforder Processors,” HP Technical report, HPL-2011-65. (This work has been adopted in the book: "Computer Architecture: A Quantitative Approach" 5th Edition)

Patents

19

Professional activities

Technical Program Committee:

  • ISLPED 2013

Conference Session Chair:

  • ICCAD 2012 

Keynote speeches: 

  • 7th Annual Workshop on Modeling, Benchmarking and Simulation (MoBS), 2011

Invited reviewer for various international conferences and journals
Invited talks on various international conferences and seminars

Intern mentored:
I have been fortunate to work with top notch interns who also made research enjoyable.

  • Ke Chen (University of Notre Dame),
  • Jishen Zhao (Pennsylvania State University)
  • Mingyu Gao (Stanford University)