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Hewlett
Packard Research Labs Fax: (650) 857-7029 Email:
Partha.ranganathan@hp.com
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Parthasarathy
Ranganathan (Partha) http://www.hpl.hp.com/personal/Partha_Ranganathan/ |
Home
Email: Partha@gmail.com |
Research
Interests
Computer architecture, parallel and distributed
computing
Key projects
·
Blades++ (TCO-aware next-generation blade systems)
·
SmartPower (power-efficient high-performance system, power modeling)
·
RSIM (system evaluation
& architectures for media and database applications)
Education
Ph.D.,
May 2000, Electrical and Computer Engineering,
Design
of General-Purpose Systems for Emerging Applications
M.S.,
1997, Electrical and Computer Engineering,
An
Evaluation of Memory Consistency Models for Shared-Memory Systems with ILP
Processors
B.Tech., 1994, Electrical Engineering,
Indian Institute of Technology (IIT),
Employment
History
Hewlett Packard Labs/Compaq
Western Research Lab, 2000—current
Principal research scientist,
2004-current
Senior research scientist, 2003-
2004
Research scientist/Member
Technical Staff, 2000- 2003
Research Assistant, Rice
University, 1995-2000
Research Intern, Digital Western
Research Laboratory, Summer 1997
Research Intern, Digital Western
Research Laboratory, Summer 1996
Awards and
Recognition
·
Technology
review top 35 young innovators, 2007
·
ESSL
Research Leadership Award “for achieving
recognition as a power management expert in the HP internal and external system
architecture community”, December 2006, Awarded to one person at the lab
level
·
IEEE
Senior Member, August 2006, ACM Senior Member, December 2006
·
Hewlett
Packard e-Award, in recognition of
creating a virtual team to overcome international and organizational boundaries
while combining two unique technology areas, namely user interfaces and low
power design for new HP PDA products, April 2004
·
Alumni Acknowledgement Award, Indian Institute of
Technology,
·
Alumni Service Award, IIT
·
Lodeiska
Stockbridge Vaughan Fellowship, for outstanding
achievement and promise, 1996-1997
(awarded to one graduate student from all departments in the Rice School of Engineering.)
·
·
Government of
Selected Press Features
(30+ interviews and features, in magazines and
newspapers in North America, South America, Asia, and
·
Benchmarking Power-Efficient Servers",
Slashdot, 8/21/07
·
HP researcher achieves victory in power struggle,
EE times, August 2007
·
“Future stock”, Times of
·
MIT’s Tech Review Honors Young Energy Stars,
earth2tech.com
·
Building an energy efficient home computer,
blogs.zdnet.com, September 2007
·
HP's
·
HP Global Citizenship Report, 2006
·
MIT Technology Review
“The heat
is off!” – featured in new ideas for revolutionary technology, July 2005
“Energy-saving
screens,” December 2004
·
Mobile PC, "Fade
to gray," November 2004
·
Business
Week, “The Race for Brawnier Batteries,”
June 2004
·
Power Electronics Technology, “Smarter Power Management Techniques Promise More Power for Portables,”
September 2004
·
Lead
feature in San Francisco Chronicle Business Section
“HP
tests tactics to save batteries,” September 2004
·
Web features
Slashdot and Tom’s hardware guide, March 2005 (250+
responses)
Hp.com, physorg.com, News.PDA Live!, PDAlive.com, davesipaq.com
·
Non-english language features (translation available off google)
(French) L’Ordinateur individual, March 2005
(Italian) Se Consumi Ti SpengoSE,
WellcomeNews, March 2005
(Swedish) Forskning & Framsteg,
March 2005
(Brazilian) A arte de economizar energia em portáteis,
Jornal do Brasil, March 2005
(German) Neue Displays
verbrauchen weniger Strom, Welt am Sonntag, January 2005
(Dutch) ArtikelAG, "PDA kan mit minder energy," December 2004
Research
Contributions
Power- and energy-efficiency. My recent research focuses
on designing power- and energy-efficient systems for future computing
environments (from small mobile devices to dense servers in data centers). Some of the contributions of this work
include: Energy-adaptive displays and
energy-aware user interfaces that pioneered the notion of displays that
adapt their energy consumption based on scope of user interest; this improves
display battery usage two-fold to twenty-fold. Heterogeneous multi-core architectures that propose the use of core
diversity in chip multiprocessor to match workload requirements to
architectural power efficiency; this enables two-fold to ten-fold improvements
in processor power. Power-aware blade
architectures that propose the notion of power budget enforcement at the
enclosure level through hardware-software co-ordination to leverage variations
in typical usage patterns; this improves blade power budgets by a factor of two.
Facilities-aware data center resource
provisioning solutions that adapt workload scheduling to optimize for power
and cooling costs in addition to performance; for example, temperature-aware
resource scheduling can reduce annual cooling costs (often millions of dollars)
in large data centers by half. Our work
has also developed several new approaches for power measuring and monitoring,
including JouleSort,
energy-based statistical profiling,
location-aware knowledge planes, as well as proxy-based environmental modeling. Using these tools, we have also
performed several detailed studies (often the first such in the literature) of
power consumption of real system deployments, and have influenced industry
standards and metrics.
High-performance and better
programmability. My dissertation research focused on application-optimized
architecture designs in response to changes in the application mix favoring
database, media, and communication applications, as well as improvements to
performance, programmability, and simulation of multiprocessor systems enabled
by the emergence of processors that aggressively leveraged instruction-level
parallelism (ILP). Specific
optimizations that emerged out of this work include reconfigurable caches – a design that enabled on-the-fly reuse of
otherwise under-utilized memory resources,
Patents
More than 42 patents
pending or issued. Please see
Keynotes, Panels,
and Tutorials
1.
Low-Power
PDA displays, Keynote feature presentation at PortablePower, 2004
2.
The
Power Management Challenge: Getting the Next 100X,
Keynote presentation at the 2nd workshop on optimizations for DSPs and Embedded Systems, 2004
3.
Panel Participation:
o
“Energy-efficient Next-Generation Data Centers for
Sustainable Business Outcomes”, HP Press Panel, July 2007
o
National Science Foundation, Computer systems
panel, January 2007
o
National Science Foundation, Computer systems
panel, September 2005
o
Panel – “Important Research Challenges in
Temperature-aware Computer Systems”, TACS, June 2005
o
Panel – “New Products and Applications”, PortablePower 2004
o
National Science Foundation, Computer systems
panel, June 2004
o
National Science Foundation, Computer systems
panel, February 2003
o
Round-table
discussion on ``Limits and Future'', Workshop on Mixing Logic and DRAM: Chips
that Compute and Remember,
4.
Tutorials
o
Enterprise Power and Cooling: A chip-to-datacenter
perspective, HotChips 2007
o
Enterprise Power and Cooling: A chip-to-datacenter
perspective, ASPLOS 2006
Book
1.
Parthasarathy
Ranganathan and T. N. Vijaykumar, “Power-aware
computer architectures: from chips to data centers,” Morgan Kaufmann, Under
development, due to appear December 2008
Publications (copies available from http://www.hpl.hp.com/personal/Partha_Ranganathan)
Under
preparation/review
2.
"Microblades
and Megaservers: Server Architectures for Emerging Warehouse-Computing
Environments," Kevin Lim, Parthasarathy Ranganathan, Jichuan Chang, Chandrakant Patel, Trevor Mudge,
Steve Reinhardt, 2007
3.
"Implementing
High-Availability Memory with a Duplication Cache," Nidhi
Aggarwal, Norman Jouppi, Parthasarathy Ranganathan, Jim
Smith, Kewal Saluja, 2007
4.
"Defining
and Evaluating Metrics for Manageability Efficiency," Jacob Leverich, Vanish Talwar, Parthasarathy Ranganathan,
Christos Kozyrakis, 2007
5.
"M-Channels
and M-Brokers: New Abstractions for Co-ordinated
Management in Virtualized Systems," Sanjay Kumar, Vanish Talwar, Parthasarathy Ranganathan, Karsten Schwan, Ripal Nathuji,
2007
6.
“COVERT:
Configurable Virtual Redundancy with Transparent Availability on Commodity
Software,” Nidhi Aggarwal,
Norman Jouppi, Parthasarathy
Ranganathan, Jim Smith, Kewal
Saluja, 2007
7.
"Active
Storage Revisited: The Case for Power and Performance Benefits for Unstructured
Data Processing Applications," Shahrukh Tarapore, Clint Smullen, Sudhanva Gurumurthi, Parthasarathy Ranganathan,
Mustafa Uysal, 2007 [pdf]
8.
“Coevolution of Operating Systems and Asymmetric Single-ISA CMPs,” Nathan Binkert, Jeffrey C.
Mogul, Jayaram Mudigonda,
Parthasarathy Ranganathan, Vanish Talwar, 2007 [pdf]
9.
“Closely
Coupled Operating System Pairs for Emerging Manageability Architectures,”
Vanish Talwar and Parthasarathy Ranganathan, 2007 [pdf]
Reviewed
publications
10.
No
Power Struggles: A Unified Multi-level Power Management Architecture for the
Data Center, Ramya Raghavendra,
Parthasarathy Ranganathan,
Vanish Talwar, Zhikui Wang,
and Xiaoyun Zhu, Proceedings of the
International Conference on Architectural Support for Programming Languages and
Operating Systems (ASPLOS), March 2008
11.
“Fabric
convergence and implications for next-generation blade servers”, Kevin Leigh, Parthasarathy
Ranganathan, Jaspal Subhlok, , Proceedings
of the International Conference on High-Performance Computer Architecture
(HPCA), February 2008
12.
Modeling
and Metrology Challenges for Enterprise Power Management , Suzanne Rivoire, Mehul Shah, Parthasarathy Ranganathan,
Christos Kozyrakis, Justin Meza, IEEE Computer, December 2007
13.
Cost-aware
Scheduling for Heterogeneous Enterprise Machines (CASH’EM),” Jennifer Burge,
Parthasarathy Ranganathan, Janet L. Wiener, GreenCom, September 2007 [pdf]
14.
“Isolation
in Commodity Multicore Processors,” Nidhi Aggarwal, Parthasarathy
Ranganathan, Norman P. Jouppi, James E. Smith, IEEE Computer, June 2007 (cover
feature) [pdf]
15.
“JouleSort: A Balanced Energy-Efficiency Benchmark,”
16.
“Configurable
Isolation: Building High Availability Systems with Commodity Multi-Core
Processors,“ Nidhi Aggarwal,
Parthasarathy Ranganathan, Norman Jouppi, James
Smith, Proceedings of the International
Symposium on Computer Architecture (ISCA), June 2007 [pdf]
17.
"Motivating
Commodity Multi-Core Processor Designs for System-level Error Protection,"
Nidhi Aggarwal, Parthasarthy Ranganathan, Norman P. Jouppi,
James E. Smith, George Krejcki, and Kewal K. Saluja, Proceedings of the 2007 IEEE Workshop on Silicon
Errors in Logic - System Effects, April 2007 [pdf]
18.
“No Power Struggles: A Unified Power
Management Architecture for the Data Center,” Ramya Raghavendra, Parthasarathy Ranganathan, Xiaoyun
Zhu, and Zhikui Wang, Proceedings of HP Techcon, April 2007
[hp-pdf]
19.
“General-Purpose Blade Infrastructure for
Configurable System Architectures,” Kevin Leigh, Parthasarathy Ranganathan, Jaspal Subhlok, Journal on Parallel and Distributed
Databases (JPDD), Springer Publishers 0926-8782 (Print) 1573-7578 , March
2007 [pdf]
(Also available as HPL Tech Report)
20.
"Simulating
Complex Enterprise Workloads using Utilization Traces," Parthasarathy
Ranganathan and Philip Leech, Tenth
Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW),
held with HPCA-13, February 2007 [pdf]
21.
“Full-system
Power Analysis and Modeling for Server Environments,” Dimitris
Economous,
22.
“Ensemble-level
Power Management for Dense Blade Servers,” Parthasarathy Ranganathan, Phil
Leech, David Irwin, and Jeff Chase, Proceedings
of the International Symposium on Computer Architecture (ISCA), June 2006 [pdf]
23.
“ConSil: Low-cost Thermal Mapping of Data Centers,” Justin
Moore, Jeff Chase, and Parthasarathy Ranganathan. First Workshop on Tackling Computer Systems Problems with Machine
Learning Techniques (SysML), June, 2006 [pdf]
24.
“Weatherman:
Automated, Online, and Predictive Thermal Mapping and Management for Data
Centers,” Justin Moore, Jeff Chase, and Parthasarathy Ranganathan, Proceedings of the Third International Conference
on Autonomic Computing (ICAC), June 2006 [pdf]
25.
“PowerBalancing for Future-generation Blades,” Hernan Laffitte, Phil Leech,
Parthasarathy Ranganathan, Charlie Shaver, Khaldoun Alzien, Proceedings
of HP Techcon, April 2006 [hp-pdf]
26.
“Energy-aware
user interfaces and energy-adaptive displays,” Parthasarathy Ranganathan, Erik Geelhoed, Meera Manahan, and Ken
Nicholas, IEEE Computer, March 2006 (cover feature) [pdf]
27.
“IT
Infrastructure in Emerging Markets: Arguing for an End-to-end Perspective,”
Ajay Gupta, Parthasarathy Ranganathan, Prashant Sarin, and Mehul Shah, IEEE Pervasive, April 2006 (cover feature) [pdf]
28.
“Heterogeneous
chip multiprocessors,” Rakesh Kumar, Dean Tullsen, Norman Jouppi,
Parthasarathy Ranganathan, IEEE Computer,
November 2005 (cover feature)
[pdf]
29.
“Dense
and smart: Hardware-software co-ordination for blade server power reduction,” Parthasarathy
Ranganathan et al, Proceedings of HP TechCon, March 2005. [hp-pdf]
30.
“Making
Scheduling Cool: Temperature-aware Resource Scheduling,” Justin Moore,
31.
“Enterprise
IT trends and implications on system architecture research,” Parthasarathy
Ranganathan and Norman Jouppi, Proceedings of the International Conference on High-Performance
Computer Architecture (HPCA), 2005 [pdf]
32.
“
33.
“Going Beyond CPUs: The Potential of
34.
Investigating the Relationship Between Battery Life
and User Acceptance of Dynamic, Energy-Aware Interfaces on Handhelds, Lance
Bloom, Rachel Harter, Erik Geelhoed, Meera Manahan, and Parthasarathy Ranganathan, Proceedings of MobileHCI
2004, March 2004 [pdf]
35.
Energy-adaptive Displays and Energy-aware User
Interfaces, Parthasarathy Ranganathan, Erik Geelhoed,
Meera Manahan, and
36.
Design Principles for Energy-aware Displays on
OLED-based Systems, Sander Vroegindeweij, Rachel
Harter, Erik Geelhoed, and Parthasarathy Ranganathan,
Second International Conference on
Appliance Design (2AD), May 2004 [pdf]
37.
Single-ISA
Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance,,
Rakesh Kumar,
38.
Energy-aware User Interfaces: An Evaluation of User
Acceptance, Tim Harter, Sander Vroegindeweij, Erik Geelhoed, Meera Manahan, and
Parthasarathy Ranganathan, Proceedings of
Conference on Human Factors in Computing Systems (CHI), April 2004 [pdf]
39.
Single-ISA Heterogeneous Multi-Core Architectures:
The Potential for Processor Power Reduction. Rakesh
Kumar, Dean Tullsen, Parthasarathy Ranganathan, and
40.
Energy consumption in mobile devices: Why Future
Systems Need Requirements-Aware Energy Scale-Down, Robert Mayo and
Parthasarathy Ranganathan, Lecture Notes in Computer Science (LCNS),
special issue on power management, 2003. [pdf] (A
preliminary version of this paper appeared in the Proceedings of the Workshop
on Power Aware Computing Systems (PACS), December 2003 [pdf],
and as Hewlett Packard Technical Report HPL 2003-167)
41.
A Multi-Core Approach to Addressing the
Energy-Complexity Problem in Microprocessors, Rakesh
Kumar,
42.
Processor Power Reduction Via Single-ISA
Heterogeneous Multi-Core Architectures, Rakesh Kumar,
43.
44.
Energy-Adaptive Display
System Design for Future
45.
Energy-driven Statistical Profiling: Detecting
Software Hotspots, Fay Chang,
46.
RSIM: Simulating Shared-Memory Multiprocessors with
ILP Processors, C. J. Hughes, V. S. Pai, P.
Ranganathan, and S. V. Adve, IEEE Computer, vol.
29, no. 12, special issue on high performance simulators, February 2002, 40-49 [pdf]
47.
Reconfigurable Cache and their Application to Media
Processing, Parthasarathy Ranganathan, Sarita Adve, and Norman P. Jouppi, Proceedings
of the 27th International Symposium on Computer Architecture (ISCA-27),
June 2000. [pdf]
48.
Performance of Image and Video Processing with
General-Purpose Processors and Media ISA Extensions , Parthasarathy
Ranganathan, Sarita Adve,
and Norman P. Jouppi, Proceedings of the
26th International Symposium on Computer Architecture (ISCA-26), May 1999. [pdf]
49.
The Impact of Exploiting Instruction-Level
Parallelism on Shared-Memory Multiprocessors , Vijay.
S. Pai, Parthasarathy Ranganathan, Hazim Abdel-Shafi, and Sarita Adve, IEEE
Transactions on Computers (TOC), special issue on caches, February 1999,
218-226. [pdf]
50.
Recent Advances in Memory Consistency Models for
Hardware Shared-Memory Systems, Sarita Adve, Vijay S. Pai, and
Parthasarathy Ranganathan, Proceedings of the IEEE, special issue on
distributed shared-memory, March 1999, 445-455. (Was featured on IEEE front
page.) [pdf]
51.
The Relative Importance of Memory Latency,
Bandwidth, and Branch Limits to Performance, Norman P. Jouppi
and Parthasarathy Ranganathan, Proceedings
of the Workshop on Mixing Logic and DRAM: Chips that Compute and Remember.
June 1997. [pdf]
An extended version with additional data appears as “Exploiting Performance
Limits to Future Instruction-level Parallel Processors,” Parthasarathy
Ranganathan, Norman P. Jouppi and