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Hewlett
Packard Research Labs Fax: (650)
857-7029 Email:
Partha.ranganathan@hp.com
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Parthasarathy
Ranganathan (Partha) http://www.hpl.hp.com/personal/Partha_Ranganathan/ |
Home
Email: Partha@gmail.com |
Research
Interests
Computer systems architecture and
management, power efficiency, parallel and distributed computing
Key
projects
·
Blades++ and exascale datacenters (TCO-aware next-generation blade systems)
·
SmartPower (power-efficient high-performance system, power
modeling)
·
RSIM (system
evaluation & architectures for media and database applications)
Education
Ph.D.,
May 2000, Electrical and Computer Engineering,
Design of General-Purpose Systems for Emerging Applications
M.S.,
1997, Electrical and Computer Engineering,
An Evaluation of Memory Consistency Models for Shared-Memory Systems with
ILP Processors
B.Tech., 1994, Electrical
Engineering, Indian Institute of Technology (IIT),
Employment
History
Hewlett Packard Labs/Compaq
Western Research Lab, 2000—current
Principal research scientist,
2004-current
Senior research scientist, 2003-
2004
Research scientist/Member
Technical Staff, 2000- 2003
Research Assistant, Rice
University, 1995-2000
Research Intern, Digital Western
Research Laboratory, Summer 1997
Research Intern, Digital Western
Research Laboratory, Summer 1996
Awards and
Recognition
·
6
internal company recognition awards
·
Rice
University Outstanding Young Engineering Alumnus, 2008, for notable accomplishments as an engineer and contributions to Rice
and the community.
·
Technology
review top 35 young innovators, 2007, who
will create the future by transforming existing industries and establishing new
ones
·
ESSL
Research Leadership Award “for achieving
recognition as a power management expert in the HP internal and external system
architecture community”, December 2006, Awarded to one person at the lab
level
·
IEEE
Senior Member, August 2006, ACM Senior Member, December 2006
·
Hewlett
Packard e-Award, in recognition of
creating a virtual team to overcome international and organizational boundaries
while combining two unique technology areas, namely user interfaces and low
power design for new HP PDA products, April 2004
·
Alumni Acknowledgement Award, Indian Institute of
Technology,
·
Alumni Service Award, IIT
·
Lodeiska Stockbridge Vaughan Fellowship, for
outstanding achievement and promise, 1996-1997
(awarded to one graduate student from all departments in the Rice School of Engineering.)
·
·
Government of
Selected Press Features
(40+ interviews and features, in magazines and
newspapers in North America, South America, Asia, and Europe)
·
“HP Labs aims at exascale
computing,” EEtimes, September, 2008
·
Hp.com patent profile (“features the company’s most creative people — the top
inventors, patent holders and engineers – and what inspires them”), August,
2008
·
“Proliferation of devices hinders energy efficiency,”
IndUS BusinessJournal, March,
2008
·
“HP Looks To Improve Power Management Coordination“,
Slashdot 3/08
·
“Looking at datacenter power of the future,” ComputerWorld, February 08
·
“Benchmarking
Power-Efficient Servers", Slashdot, 8/21/07
·
“HP researcher achieves victory in power struggle,”
EE times, August 2007
·
“Future stock”, Times of
·
“MIT’s Tech Review Honors Young Energy Stars,”
earth2tech.com
·
“Building an energy efficient home computer,”
blogs.zdnet.com, September 2007
·
“HP's Green Data Center Portfolio Keeps Growing,”
InternetNews.com, 2007
·
HP Global Citizenship Report, 2006
·
“The heat is off!” – featured in new ideas for
revolutionary technology, MIT Technology Review, July 2005
·
Slashdot
and Tom’s hardware guide, March 2005 (250+ responses)
·
Hp.com, physorg.com, News.PDA Live!, PDAlive.com, davesipaq.com.
March 2005
·
(French)
L’Ordinateur individual, March 2005
·
(Italian)
Se Consumi Ti SpengoSE, WellcomeNews,
March 2005
·
(Swedish) Forskning & Framsteg,
March 2005
·
(Brazilian) A arte
de economizar energia em portáteis, Jornal do Brasil, March
2005
·
(German) Neue Displays verbrauchen
weniger Strom, Welt am Sonntag, January 2005
·
(Dutch)
ArtikelAG, "PDA kan mit minder energy," December 2004
·
“Energy-saving screens,” MIT Technology Revie, December 2004
·
Mobile PC, "Fade
to gray," November 2004
·
Power Electronics Technology, “Smarter Power Management Techniques Promise More Power for Portables,”
September 2004
·
Lead
feature in San Francisco Chronicle Business Section, “HP tests tactics to save
batteries,” September 2004
·
Business
Week, “The Race for Brawnier Batteries,”
June 2004
·
Video
interviews
Everyday Edisons,
PBS 2008
Pod-Planet.com, “Advances in power management,”
Podcast interview, August 2007
Research
Contributions
Exascale data centers. I am the principal
investigator for the exascale datacenter project at
HP Labs. This research seeks to create and demonstrate an end-to-end data center
infrastructure solution designed ground-up with total costs of ownership and
manageability in focus. We systematically redesign individual platform elements
as efficient building blocks with their role in the broader solution in mind,
to be used in combination with a powerful management layer at the datacenter
level to dynamically monitor and manage resources for global efficiency and
improved capabilities. Sub-contributions of the project include (1) disaggregated shared platforms in
dematerialized datacenters, with powerful hardware-aware resource
management co-designed into the virtualization layer, (2) connected by an end-to-end networking architecture,
spanning vNICs to switches, providing QoS management over converged fabrics, (3) with rich management
and platform capabilities delivered through a ecosystem of virtual appliances
driven by powerful abstractions for cross-layer
communication and coordination.
Power- and energy-efficiency. My recent research
focuses on designing power- and energy-efficient systems for future computing
environments (from small mobile devices to dense servers in data centers). Some of the contributions of this work
include: Energy-adaptive displays and
energy-aware user interfaces that pioneered the notion of displays that
adapt their energy consumption based on scope of user interest; this improves
display battery usage two-fold to twenty-fold. Heterogeneous multi-core architectures that propose the use of core
diversity in chip multiprocessor to match workload requirements to
architectural power efficiency; this enables two-fold to ten-fold improvements
in processor power. Power-aware blade
architectures that propose the notion of power budget enforcement at the
enclosure level through hardware-software co-ordination to leverage variations
in typical usage patterns; this improves blade power budgets by a factor of
two. Facilities-aware data center
resource provisioning solutions that adapt workload scheduling to optimize
for power and cooling costs in addition to performance; for example,
temperature-aware resource scheduling can reduce annual cooling costs (often
millions of dollars) in large data centers by half. Our work has also developed several new
approaches for power measuring and monitoring, including JouleSort, energy-based statistical profiling, location-aware knowledge planes,
as well as proxy-based environmental
modeling. Using these tools, we have also performed several detailed
studies (often the first such in the literature) of power consumption of real system
deployments, and have influenced industry standards and metrics.
High-performance and
better programmability. My dissertation research focused on
application-optimized architecture designs in response to changes in the
application mix favoring database, media, and communication applications, as
well as improvements to performance, programmability, and simulation of
multiprocessor systems enabled by the emergence of processors that aggressively
leveraged instruction-level parallelism (ILP).
Specific optimizations that emerged out of this work include reconfigurable caches – a design that
enabled on-the-fly reuse of otherwise under-utilized memory resources,
Patents
More than 50
patents pending or issued. Please see
Keynotes,
Panels, and Tutorials
1.
Designing servers and datacenters for the exascale computing era, Keynote presentation at the Rice University
Industrial Affiliates Meeting, 2008
2.
System implications of integrated photonics
(with Norm Jouppi), International
Symposium on Low Power Electronics, September, 2008
3.
Low-Power PDA displays, Keynote
feature presentation at PortablePower 2004
4.
The Innovation Process, with the exascale datacenter as a case study, HP GDIC Innovation Symposium, August 2008
5.
The Power Management Challenge: Getting the Next 100X, Keynote presentation at the 2nd workshop on optimizations
for DSPs and Embedded Systems, 2004
6.
Panel Participation:
o
Towards
a zero-carbon footprint for the IT ecosystem: energy-efficient servers and
datacenters, Canada-California Strategic Innovation Partnership Green IT
workshop, 2008
o
Rethinking server design for the ensemble, Gigascale institute workshop, 2008
o
Panel Chair, “Power
management from cores to datacenters: where are we going to get the next 10X?”,
ISLPED 2008
o
Exascale Software Challenges DARPA white paper, July 2008
o
National Science Foundation, Computer systems
panel, April 2008
o
“Energy-efficient Next-Generation Data Centers for
Sustainable Business Outcomes”, HP Press Panel, July 2007
o
National Science Foundation, Computer systems
panel, January 2007
o
National Science Foundation, Computer systems
panel, September 2005
o
Panel – “Important Research Challenges in
Temperature-aware Computer Systems”, TACS, June 2005
o
Panel – “New Products and Applications”, PortablePower 2004
o
National Science Foundation, Computer systems
panel, June 2004
o
National Science Foundation, Computer systems
panel, February 2003
o
Round-table
discussion on ``Limits and Future'', Workshop on Mixing Logic and DRAM: Chips
that Compute and Remember,
7.
Tutorials
o
Enterprise Power and Cooling: A chip-to-datacenter
perspective, HotChips 2007
o
Enterprise Power and Cooling: A chip-to-datacenter
perspective, ASPLOS 2006
Book
1. Parthasarathy
Ranganathan and T. N. Vijaykumar, “Power-aware computer architectures: from
chips to data centers,” Morgan Kaufmann, Under development, for December 2009
Publications
(copies available from http://www.hpl.hp.com/personal/Partha_Ranganathan)
Under preparation/review
2.
“Power-aware computing principles,”
Parthasarathy Ranganathan, CACM 2008 [pdf]
3.
“A
Comparison of High-Level Full-System Power Models,” Suzanne Rivoire,
Parthasarathy Ranganathan, Christos Kozyrakis, 2008 [pdf]
4.
“Delivering Energy Proportionality with Non
Energy Proportional Systems – Optimizations at the Ensemble Layer,” Niraj
Tolia, Zhikui Wang, Manish Marwah, Cullen Bash, Parthasarathy Ranganathan,
Xiaoyun Zhu, 2008 [pdf]
5.
“Power Aware Design and Operation of Data
Center Networks,” Priya Mahadevan, Puneet Sharma, Sujata Banerjee, Partha
Ranganathan, 2008 [pdf]
6.
“Tracking the Power in an Enterprise Decision
Support System,” Justin Meza, Mehul A. Shah, Parthasarathy Ranganathan, Mike
Fitzner, Jay Veazey, 2008 [pdf]
7.
“Motivating
integrated switch and NIC functionality for future manycore
servers,” J. Mudigonda et al, 2008 [pdf]
8.
“Micromanagers:
Platforms for Manageability in Future Virtualized Multicore
Environments,” Jacob Leverich et al, 2008 [pdf]
9.
“Slice
and Share: Memory disaggregation for consolidation and cost-effectiveness”,
Kevin Lim et al, 2008 [pdf]
10. “Zephyr, Hot and
Cold: Unified power and cooling management for the datacenter”, Niraj Tolia, Zhikui Wang, Manish Marwah,
Cullen Bash, Parthasarathy Ranganathan, Xiaoyun Zhu, 2008 [pdf]
11. "vManage: Coordinated Cross-layer Management in Virtualized
Systems," Sanjay Kumar, Vanish Talwar, Vibhore Kumar, Parthasarathy
Ranganathan, Karsten Schwan, 2008 [pdf]
12. “COVERT:
Configurable Virtual Redundancy with Transparent Availability on Commodity
Software,” Nidhi Aggarwal, Norman Jouppi, Parthasarathy Ranganathan, Jim Smith,
Kewal Saluja, 2008 [pdf]
13. "Defining and Evaluating Metrics for
Manageability Efficiency," Jacob Leverich, Vanish Talwar, Parthasarathy
Ranganathan, Christos Kozyrakis, 2007 [pdf]
14. “Closely Coupled Operating System Pairs for
Emerging Manageability Architectures,” Vanish Talwar and Parthasarathy
Ranganathan, 2007 [pdf]
Reviewed publications
15. “Power modeling and
measurement,” Parthasarathy Ranganathan, Suzanne Rivoire, Justin Moore, Advances in Computers, Elsevier, Book
Chapter, 2008 [pdf]
16. "Implementing
High-Availability Memory with a Duplication Cache," Nidhi Aggarwal, Norman
Jouppi, Parthasarathy Ranganathan, Jim Smith, Kewal Saluja, Annual
IEEE/ACM International Symposium on Microarchitecture,
December 2008 [pdf]
17. “M-Channels and M-Brokers: Coordinated
Management in Virtualized Systems,” Sanjay Kumar, Vanish Talwar, Parthasarathy
Ranganathan, Ripal Nathuji,
Karsten Schwan, Workshop on Managed
Multi-Core Systems (MMCS), June 2008
[pdf]
18. “Feedback Control
Algorithms for Power Management of Servers,” Zhikui Wang et al, Third International Workshop on Feedback Control Implementation and
Design in Computing Systems and Networks (FeBID),
June 2008 [pdf]
19. “vManage:
Coordinated Management in Virtualized Systems,” Sanjay Kumar, Vanish Talwar, Parthasarathy
Ranganathan, Karsten Schwan, Third
Workshop on Hot Topics in Autonomic Computing (HotAC),
April 2008 [pdf]
20. “Coevolution
of Operating Systems and Asymmetric Single-ISA CMPs,” Nathan Binkert, Jeffrey
C. Mogul, Jayaram Mudigonda, Parthasarathy Ranganathan, Vanish Talwar, IEEE Micro, 2008 [pdf]
21. "Microblades
and Megaservers: Server Architectures for Emerging Warehouse-Computing
Environments,", Reza Bacchus,
Jichuan Chang, Tom Flynn, Kevin Lim,
Chandrakant Patel, Parthasarathy Ranganathan, Robert Van Cleve, Proceedings of Techcon,
May 2008 [hp-pdf]
22. Understanding and
Designing New Server Architectures for Emerging Warehouse-Computing
Environments, Kevin Lim, Parthasarathy Ranganathan, Jichuan Chang, Chandrakant
Patel, Trevor Mudge, Steve Reinhardt, Proceedings
of the International Conference on Computer Architecture (ISCA), June 2008 [pdf]
23. Active Storage
Revisited: The Case for Power and Performance Benefits for Unstructured Data
Processing Applications , Clint Smullen, Shahrukh Tarapore, Sudhanva
Gurumurthi, Parthasarathy Ranganathan, Mustafa Uysal, ACM Computing Frontiers , May, 2008 [pdf]
24. Reducing Overhead
for Soft Error Coverage in High Availability Systems. Nidhi Aggarwal, Norman P.
Jouppi, Parthasarathy Ranganathan, James E. Smith, Kewal
K. Saluja. Proceedings of the 4th Workshop on Silicon
Errors in Logic System Effects (SELSE-4), March 2008. [pdf]
25. No Power Struggles:
A Unified Multi-level Power Management Architecture for the
26. “Fabric convergence
and implications for next-generation blade servers”, Kevin Leigh, Parthasarathy Ranganathan,
Jaspal Subhlok, , Proceedings of the
International Conference on High-Performance Computer Architecture (HPCA), February
2008 [pdf]
27. Modeling and
Metrology Challenges for Enterprise Power Management , Suzanne Rivoire, Mehul
Shah, Parthasarathy Ranganathan, Christos Kozyrakis, Justin Meza, IEEE Computer, December 2007 [pdf]
28. Cost-aware
Scheduling for Heterogeneous Enterprise Machines (CASH’EM),” Jennifer Burge,
Parthasarathy Ranganathan, Janet L. Wiener, GreenCom, September 2007 [pdf]
29. “Isolation in Commodity
Multicore Processors,” Nidhi Aggarwal, Parthasarathy
Ranganathan, Norman P. Jouppi, James E.
Smith, IEEE Computer, June 2007 (cover feature) [pdf]
30. “JouleSort:
A Balanced Energy-Efficiency Benchmark,”
31. “Configurable
Isolation: Building High Availability Systems with Commodity Multi-Core
Processors,“ Nidhi Aggarwal, Parthasarathy Ranganathan, Norman Jouppi, James
Smith, Proceedings of the International
Symposium on Computer Architecture (ISCA), June 2007 [pdf]
32. "Motivating
Commodity Multi-Core Processor Designs for System-level Error Protection,"
Nidhi Aggarwal, Parthasarthy Ranganathan, Norman P.
Jouppi, James E. Smith, George Krejcki, and Kewal K. Saluja, Proceedings of the 2007 IEEE Workshop on Silicon
Errors in Logic - System Effects, April 2007 [pdf]
33. “No Power Struggles: A Unified Power Management
Architecture for the Data Center,” Ramya Raghavendra,
Parthasarathy Ranganathan, Xiaoyun Zhu, and Zhikui Wang, Proceedings of HP Techcon, April 2007
[hp-pdf]
34. “General-Purpose Blade Infrastructure for
Configurable System Architectures,” Kevin Leigh, Parthasarathy Ranganathan,
35. "Simulating
Complex Enterprise Workloads using Utilization Traces," Parthasarathy
Ranganathan and Philip Leech, Tenth
Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW),
held with HPCA-13, February 2007 [pdf]
36. “Full-system Power
Analysis and Modeling for Server Environments,” Dimitris Economous,
37. “Ensemble-level
Power Management for Dense Blade Servers,” Parthasarathy Ranganathan, Phil
Leech, David Irwin, and Jeff Chase, Proceedings
of the International Symposium on Computer Architecture (ISCA), June 2006 [pdf]
38. “ConSil:
Low-cost Thermal Mapping of Data Centers,” Justin Moore, Jeff Chase, and
Parthasarathy Ranganathan. First Workshop
on Tackling Computer Systems Problems with Machine Learning Techniques (SysML), June, 2006 [pdf]
39. “Weatherman:
Automated, Online, and Predictive Thermal Mapping and Management for Data
Centers,” Justin Moore, Jeff Chase, and Parthasarathy Ranganathan, Proceedings of the Third International
Conference on Autonomic Computing (ICAC), June 2006 [pdf]
40. “PowerBalancing
for Future-generation Blades,” Hernan Laffitte, Phil Leech, Parthasarathy Ranganathan, Charlie
Shaver, Khaldoun Alzien, Proceedings of
HP Techcon, April 2006 [hp-pdf]
41. “Energy-aware user
interfaces and energy-adaptive displays,” Parthasarathy Ranganathan, Erik Geelhoed, Meera Manahan, and Ken
Nicholas, IEEE Computer, March 2006 (cover feature) [pdf]
42. “IT Infrastructure
in Emerging Markets: Arguing for an End-to-end Perspective,” Ajay Gupta,
Parthasarathy Ranganathan, Prashant Sarin, and Mehul Shah, IEEE
Pervasive, April 2006 (cover
feature) [pdf]
43. “Heterogeneous chip
multiprocessors,” Rakesh Kumar, Dean Tullsen, Norman Jouppi, Parthasarathy
Ranganathan, IEEE Computer, November
2005 (cover feature) [pdf]
44. “Dense and smart:
Hardware-software co-ordination for blade server power reduction,” Parthasarathy
Ranganathan et al, Proceedings of HP TechCon, March 2005. [hp-pdf]
45. “Making Scheduling
Cool: Temperature-aware Resource Scheduling,”
46. “Enterprise IT
trends and implications on system architecture research,” Parthasarathy
Ranganathan and Norman Jouppi, Proceedings
of the International
47. “
48. “Going Beyond CPUs: The Potential of
49. Investigating the Relationship Between Battery Life and User Acceptance
of Dynamic, Energy-Aware Interfaces on Handhelds, Lance Bloom, Rachel Harter,
Erik Geelhoed, Meera
Manahan, and Parthasarathy Ranganathan, Proceedings
of MobileHCI 2004, March 2004 [pdf]
50. Energy-adaptive Displays and Energy-aware User Interfaces, Parthasarathy
Ranganathan, Erik Geelhoed, Meera
Manahan, and
51. Design Principles for Energy-aware Displays on OLED-based Systems,
Sander Vroegindeweij, Rachel Harter, Erik Geelhoed, and Parthasarathy Ranganathan, Second International
52. Single-ISA Heterogeneous Multi-Core
Architectures for Multithreaded Workload Performance,, Rakesh Kumar,
53. Energy-aware User Interfaces: An Evaluation of User Acceptance, Tim
Harter, Sander Vroegindeweij, Erik Geelhoed, Meera Manahan, and
Parthasarathy Ranganathan, Proceedings of
54. Single-ISA Heterogeneous Multi-Core Architectures: The Potential for
Processor Power Reduction. Rakesh Kumar, Dean Tullsen, Parthasarathy
Ranganathan, and
55. Energy consumption in mobile devices: Why Future Systems Need
Requirements-Aware Energy Scale-Down, Robert Mayo and Parthasarathy
Ranganathan, Lecture Notes in Computer Science (LCNS), special issue on
power management, 2003. [pdf] (A preliminary version of this paper appeared in
the Proceedings of the Workshop on Power Aware Computing Systems (PACS), December
2003 [pdf],
and as Hewlett Packard Technical Report HPL 2003-167)
56. A Multi-Core Approach to Addressing the Energy-Complexity Problem in
Microprocessors, Rakesh Kumar,
57. Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core
Architectures, Rakesh Kumar,
58.
59. Energy-Adaptive Display System Design for
Future
60. Energy-driven Statistical Profiling: Detecting Software Hotspots, Fay
Chang,
61. RSIM: Simulating Shared-Memory Multiprocessors with ILP Processors, C.
J. Hughes, V. S. Pai, P. Ranganathan, and S. V. Adve, IEEE Computer, vol.
29, no. 12, special issue on high performance simulators, February 2002, 40-49 [pdf]
62. Reconfigurable Cache and their Application to Media Processing,
Parthasarathy Ranganathan, Sarita Adve, and Norman P. Jouppi, Proceedings of
the 27th International Symposium on Computer Architecture (ISCA-27), June
2000. [pdf]
63. Performance of Image and Video Processing with General-Purpose
Processors and Media ISA Extensions , Parthasarathy Ranganathan, Sarita Adve,
and Norman P. Jouppi, Proceedings of the 26th International Symposium
on Computer Architecture (ISCA-26), May 1999. [pdf]
64. The Impact of Exploiting Instruction-Level Parallelism on Shared-Memory Multiprocessors , Vijay. S. Pai, Parthasarathy Ranganathan, Hazim Abdel-Shafi, and Sarita
Adve, IEEE Transactions on Computers (TOC), special issue on caches,
February 1999, 218-226. [pdf]
65. Recent Advances in Memory Consistency Models for Hardware Shared-Memory
Systems, Sarita Adve, Vijay S. Pai, and Parthasarathy Ranganathan, Proceedings
of the IEEE, special issue on distributed shared-memory, March 1999,
445-455. (Was featured on IEEE front page.) [pdf]
66. The Relative Importance of Memory Latency, Bandwidth, and Branch Limits
to Performance, Norman P. Jouppi and Parthasarathy Ranganathan, Proceedings of the Workshop on Mixing Logic
and DRAM: Chips that Compute and Remember. June 1997. [pdf] An
extended version with additional data appears as “Exploiting Performance Limits
to Future Instruction-level Parallel Processors,” Parthasarathy Ranganathan, Norman
P. Jouppi and
67. Performance of Database Workloads on Shared-Memory Systems with
Out-of-Order Processors, Parthasarathy Ranganathan,
68. Using Speculative Retirement and Larger Instruction Windows to Narrow
the Performance Gap between Memory Consistency Models , Parthasarathy
Ranganathan, Vijay S. Pai, and Sarita V. Adve, Proceedings of the 9th Annual
ACM Symposium on Parallel Algorithms and Architectures (SPAA-9), June 1997,
199-210. [pdf]
69. The Interaction of Software Prefetching with
ILP Processors in Shared-Memory Systems, Parthasarathy Ranganathan, Vijay S.
Pai, Hazim Abdel-Shafi, and
Sarita V. Adve, Proceedings of the 24th International Symposium on Computer
Architecture (ISCA-24), June 1997, 144-156. [pdf]
70. RSIM: An Execution-Driven Simulator for ILP-Based Shared-Memory
Multiprocessors and Uniprocessors, Vijay S. Pai,
Parthasarathy Ranganathan, and Sarita V. Adve, IEEE Technical Committee on Computer Architecture newsletter, Fall
1997. [pdf]
An earlier version of this paper appeared in the Proceedings of the 3rd
Workshop on Computer Architecture Education (held in conjunction with the 3rd
International Symposium on High Performance Computer Architecture), February 1997.
71. The Impact of Instruction-Level Parallelism on Multiprocessor
Performance and Simulation Methodolgy, Vijay S. Pai,
Parthasarathy Ranganathan, and Sarita V. Adve, Proceedings of the 3rd
International Symposium on High Performance Computer Architecture (HPCA-3),
February 1997, 72-83. Also presented at the Sixth Workshop on Shared-Memory
Multiprocessors, October 5 1996. [pdf]
72. An Evaluation of Memory Consistency Models for Shared-Memory Systems
with ILP Processors, Vijay S. Pai, Parthasarathy Ranganathan, Sarita V. Adve,
and Tracy Harton, Proceedings of the 7th
International
Other
publications
73. “MagiXen:
Combining Binary Translation and Virtualization,” Matthew Chapman, Daniel J. Magenheimer, Parthasarathy Ranganathan, Hewlett Packard Technical
Report TR2007-85,
2007 [pdf]
74. From Cores to Systems: Challenges and Opportunities for Multi-Core
Research, Norman Jouppi and Parthasarathy Ranganathan, Microsoft Multicore Workshop, January 2007 [pdf]
75. A Sense of Place: Towards a Location-aware Information Plane for
76. Idle Mode Power Management for Personal Wireless Devices, Nevine Abou-Ghazala, Robert Mayo,
and Parthasarathy Ranganathan. Hewlett
Packard Technical Report HPL 2003-102, 2003 [pdf]
77. Managing Power and Heat as First-Class Resources in Enterprise IT
environments: The SmartPower Proposition,
78. The Power of Less
Power: Benefits from a Power Management Virtual Team Across HP, Partha
Ranganathan (HPL), Christian Belady (HP-Superdome),
Heather Bean (HP-Digital Camera), Steve Chen (HP-laptop), Kevin Leigh
(HP-blade), Sam Naffziger (HP-IA64),
79. Understanding the
Importance of Power and Cooling Solutions in Data Centers: A Working Document,
Parthasarathy Ranganathan et al., Hewlett
Packard Technical Report HPL-2003-79,
April 2003 [hp-pdf]
80. Detecting Energy Hot Spots: Experiences with the iPAQ
PocketPC, Fay Chang,
81. HTTP Features for conserving energy in wireless devices, Eduardo Pinheiro,
82. General-purpose Architectures for Media Processing and Database
Applications, Parthasarathy Ranganathan, Ph.D.
Thesis, Department of Electrical and Computer Engineering, Rice University,
August 2000 [pdf]
83. An Evaluation of Memory Consistency Models for Shared-Memory Systems
with ILP Processors,
Parthasarathy Ranganathan, Master's
thesis, Department of Electrical and Computer Engineering, Rice University.
April 1997. [pdf]
84. RSIM Reference Manual Version 1.0 ,
Vijay S. Pai, Parthasarathy Ranganathan, and Sarita V. Adve, Technical Report 9705, Department of
Electrical and Computer Engineering, Rice University, August 1997. [pdf]
Software
Distributed and Supported
(available
from http://www.ece.rice.edu/~rsim)
V. S. Pai, P. Ranganathan, and S. V. Adve, RSIM (Rice
Simulator for ILP Multiprocessors), Version 1.0, August 1997. RSIM is currently
the only publicly-distributed software for simulating shared-memory
multiprocessors with state-of-the-art instruction-level-parallel (ILP)
processors, with over 2000 licenses worldwide. RSIM contains more than 51,000
lines of C++ code spread over 120 files.
1.
Exascale datacenters
-- HPL India
2008, HP STSD Distinguished Speaker Symposium 2008, BSNL, Microsoft research,
HPL China, Yahoo
research India, IBM India
2.
Power Management: getting the next 10X
-- Intel India, TCS
India, Tata CRL, IISc, IIT Madras
3.
No Power Struggles: Multi-level Federated Power Management for the Data
Center
-- ASPLOS 2008, CiscoGreenResearch Symposium 2008, IISC 2008
4.
-- ASPLOS 2006
Tutorial. Hotchips 2007 Tutorial
5.
Power management from handhelds to data centers: Chasing the next 10X.
-- HPL India,
June 2005, University of Wisconsin Madison, June 2005, University of Illinois
at Urbana-Champaign, June 2005, University of Houston, August 2006, Microsoft
Research, September 2006, University of Berkeley, October 2006
6.
-- HP, July
2005,
7.
SmartPower: Power Management and Operations Automation for
the
-- The 3rd
meeting of Critical Facilities Round Table Group, September 2003
8.
Energy consumption in mobile devices: Why Future Systems Need
Requirements-Aware Energy Scale-Down.
-- Docomo Labs, April
2004 ; Stanford University, December 2003 ; Workshop on Power-aware
Computing Systems, December 2003; University of Texas at Austin, October 2003;
Rice University, October 2003; HP Personal Systems Group colloquium, October
2003; External Computer Systems Colloquium, Hewlett Packard Labs, August 2003; Microsoft
Research Labs, July 2003; iPAQ summit, HP Labs,
Palo Alto, September 2002
9.
Energy-driven
Statistical Profiling: Detecting Software Hotspots.
-- Workshop on Power-aware Computing Systems, February 2002
10. General-Purpose Architectures for Media Processing.
--
11. Reconfigurable Caches and their Application to Media
Processing Applications.
-- 27th International Symposium on Computer Architecture (ISCA-27),
12. General-Purpose Architectures for Media Processing
Applications.
-- Computer Systems Lab, Stanford
University, May 2000, College of Computing, Georgia Institute of Technology,
May 2000, Department of Electrical and Computer Engineering, Duke University,
April 2000, Department of Computer Science, University of California at San
Diego, April 2000, Department of Electrical and Computer Science, University of
Michigan, April 2000, Department of Electrical and Computer Engineering, Purdue
University, April 2000, Microsoft Research, April 2000, Department of
Electrical and Computer Engineering, Cornell University, March 2000, Department
of Electrical and Computer Engineering, Carnegie Mellon University, March 2000,
Computer Systems Lab, Rice University, March 2000, Compaq Western Research
Labs, March 2000, Compaq Cambridge Research Labs, March 2000, Departments of
Electrical ECE and CS, University of Massachussets at
Amherst, March 2000, Compaq VSSAD Alpha Development Group, March 2000, Computer
Systems Lab, University of Rochester, February 2000, Hewlett Packard Research
Labs, February 2000, Intel Microprocessor Research Labs, February 2000, Indian
Institute of Technology (IIT), Madras. November 1999, Indian
Institute of Sciences (IISc),
13. Performance of Image and Video Processing with
General-Purpose Processors and Media ISA Extensions.
-- 26th International Symposium on Computer Architecture (ISCA-26),
14. Performance of Database Workloads on Shared-Memory
Systems with Out-of-Order Processors.
-- 8th International Conference on Architectural Support for Programming
Languages and Operating Systems (ASPLOS-VIII),
15. Interaction of Software Prefetching
with ILP Processors in Shared-Memory Systems.
--24th International Symposium on Computer Architecture (ISCA-24),
16. The Relative Importance of Memory Latency, Bandwidth,
and Branch Limits to Performance.
-- Workshop on Mixing Logic and DRAM: Chips that Compute and Remember,
17. The Impact of Instruction-Level Parallelism on
Multiprocessor Performance and Simulation Methodology.
-- 6th Workshop on Shared-Memory Multiprocessors (with ASPLOS-VII),
Other Professional
Activities
·
HPL Strategic planning committee member, Advisory
Board Observer, 2007
·
EPA Power
·
Chair, company-wide virtual community on power
management within Hewlett Packard, 2005
·
Chair, birds-of-a-feather session on power
management, HP TechCon2003
·
Conference
organization
·
Program
committee
·
Teaching
·
Mentoring
o
Summer interns
Vishaka Gupta (Georgia
Tech), Summer 2008, Kevin Lim (University of Michigan), Sanjay Kumar (Georgia
tech), Justin Meza (UCLA), Summer 2008, 2007, Jen Burge (Duke University),
Summer 2006, Ramya Raghavendra (UCSB), Summer 2006,
Nidhi Aggarwal (Wisconsin), Summer 2006, Summer 2007, Suzanne Rivoire (Stanford
University), Summer 2005; Lykomidis Mastraleon (Stanford University), Winter 2004; Dimitris
Economou (Stanford University), Summer 2004-; David Irwin (Duke University),
Spring/Summer 2004; Justin Moore (Duke University), Summer 2003, Summer 2004;
Sander Vroegindeweij, Summer 2003; Neven Abou-Ghazala (University of
Pittsburg), Summer 2002; Rakesh Kumar (University of San Diego), Summer 2002-;
Annie Luo (Carnegie Mellon University), Summer 2002; Eduardo Pinheiro (Rutgers University), Summer 2001; Aamer Jaleel
(University of Maryland), Summer 2001
o Thesis committee &
advising:
·
Reviewer for
Morgan
Kauffman book review, IEEE Computer, Journal of Parallel and Distributed
Computing, Transactions on Computers, ACM Transactions on Programming Languages
and Systems, Transactions on Parallel and Distributed Systems (03,02),
International Symposium on Computer Architecture (ISCA), International
Symposium on Microarchitecture, International
Conference on Architectural Support for Programming Languages and Operating
Systems (ASPLOS), International Symposium on High Performance Computer
Architecture, International Conference on Parallel Processing, International
Symposium on Parallel Algorithms and Architectures, International Conference on
Supercomputing, Conference on Parallel Architectures and Compilation Techniques
(PACT), EUROPAR Conference, International Conference on Performance Theory,
Measurement, and Evaluation of Computer and Communication Systems, Journal on
Current Science, Transactions on Architecture and Code Optimization (TACO),
Workshop on mobile computing systems and applications (WMCSA).
·
Senior Member of Association of Computing Machinery
(SIGARCH special interest group), IEEE (Computer Society).
·
Honorary Societies: Eta Kappa Nu (since 1995)
·
Various committee lead roles at
Other
Activities
·
Founding member, pan-IIT (www.iit.org) executive
council – Indian Institute of Technology Alumni Association, October 2002-present
·
Chair, constitution and charter definition
committee
·
Comparison of best practices of IIT associations,
white paper
·
Invited speaker, “How can Alumni make IIT’s
world-class institutes?”, IIT50,
·
Several invited talks and panels on alumni-interest
topics at venues across the country
·
IIT leadership council,
·
Chair, “Alumni Services”
·
Secretary (and Founding Director), IIT
·
Secretary, North American chapter of the IIT Madras
Alumni Association (http://www.iitmalumni.org/), 1995-1999.
·
Chair of web-page design, constitution, editorial, and strategic vision committees.
·
Founder-member, Friends of Young Minds (http://www.ruf.rice.edu/~foym).
·
·
Special-effects' staff, First Presbyterian Church
Drama Group, Fall 1994.