HP Labs Technical Reports
Click here for full text:
High-Level Synthesis of Nonprogrammable Hardware Accelerators
Schreiber, Robert; Aditya, Shail; Rau, B. Ramakrishna; Kathail, Vinod; Mahlke, Scott; Abraham, Santosh; Snider, Greg
Keyword(s): ASIC; high-level synthesis
Abstract: The PICO-N system automatically synthesizes embedded nonprogrammable accelerators to be used as co- processors for functions expressed as loop nests in C. The output is synthesizable VHDL that defines the accelerator at the register transfer level (RTL). The system generates a synchronous array of customized VLIW (very-long instruction word) processors, their controller, local memory, and interfaces. The system also modifies the user's application software to make use of the generated accelerator. The user indicates the throughput to be achieved by specifying the number of processors and their initiation interval. In experimental comparisons, PICO-N designs are slightly more costly than hand-designed accelerators with the same performance.
Back to Index