CACTI-P: Architecture-Level Modeling for SRAM-based Structures with Advanced Leakage Reduction Techniques
Li, Sheng; Chen, Ke; Ahn, Jung Ho; Brockman, Jay B.; Jouppi, Norman P.;
Keyword(s): Leakage power management; power-gating; circuit modeling; SRAM; cache; manycore processor
Abstract: This paper introduces CACTI-P, the first architecture- level integrated power, area, and timing modeling framework for SRAM-based structures with advanced leakage power reduction techniques. CACTIP supports modeling of major leakage power reduction approaches including power-gating, long channel devices, and Hi-k metal gate devices. Because it accounts for implementation overheads, CACTI-P enables indepth study of architecture-level tradeoffs for advanced leakage power management schemes. We illustrate the potential applicability of CACTIP in the design and analysis of leakage power reduction techniques of future manycore processors by applying nanosecond scale power-gating to different levels of cache for a 64 core multithreaded architecture at the 22nm technology. Combining results from CACTI-P and a performance simulator, we find that although nanosecond scale power-gating is a powerful way to minimize leakage power for all levels of caches, its severe impacts on processor performance and energy when being used for L1 data caches make nanosecond scale power-gating a better fit for caches closer to main memory.
Additional Publication Information: Published in ICCAD 2011: IEEE/ACM International Conference on Computer-Aided Design
External Posting Date: September 6, 2012 [Fulltext]. Approved for External Publication
Internal Posting Date: September 6, 2012 [Fulltext]