Technical Reports

HPL-2012-188

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System Implications of Memory Reliability in Exascale Computing

Li, Sheng; Chen, Ke; Hsieh, Ming-Yu; Muralimanohar, Naveen; Kersey, Chad D.; Brockman, Jay B.; Rodrigues, Arun F.; Jouppi, Norman P.;
HP Laboratories

HPL-2012-188

Keyword(s): Exascale computing; memory system; reliability; DRAM; ECC; chipkill; BCH; checkpointing; tagged memory

Abstract: Resiliency will be one of the toughest challenges in future exascale systems. Memory errors contribute more than 40% of the total hardware-related failures and are projected to increase in future exascale systems. The use of error correction codes (ECC) and checkpointing are two effective approaches to fault tolerance. While there are numerous studies on ECC or checkpointing in isolation, this is the first paper to investigate the combined effect of both on overall system performance and power. Specifically, we study the impact of various ECC schemes (SECDED, BCH, and chipkill) in conjunction with checkpointing on future exascale systems. Our simulation results show that while chipkill is 13% better for computation-intensive applications, BCH has a 28% advantage in system energy-delay product (EDP) for memory-intensive applications. We also propose to use BCH in tagged memory systems with commodity DRAMs where chipkill is impractical. Our proposed architecture achieves 2.3x better system EDP than state-of-the-art tagged memory systems.

12 Pages

Additional Publication Information: Published in SC 2011: International Conference for High Performance Computing, Networking, Storage and Analysis (SC11)

External Posting Date: September 6, 2012 [Fulltext]. Approved for External Publication
Internal Posting Date: September 6, 2012 [Fulltext]

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