HP Labs Technical Reports



A 1.5 Gb/s Link Interface Chipset For Computer Data Transmission

Walker, Richard C.; Hornak, Tom; Yen, Chu-Sun; Doernberg, Joey; Springer, Kent

HPL-90-105

Keyword(s):

Abstract: A set of four ICs provide encoding, multiplexing, clock extraction/demultiplexing and decoding for gigabit- rate serial data transmission. These chips form a high bandwidth data link for point-to-point communication. A new line code is implemented that provides DC balance, efficient encoding, framing, and simple clock extraction. Embedded in the code is a fixed transition used by the phase/frequency locked loop (PLL) for simple clock extraction and frame synchronization. Unlike other links, our PLL requires no trimming for data retiming, either in production or later. An on-chip voltage-controlled oscillator (VCO) with a tuning range of 1.1 to 1.6 GHz is available for use with the PLL. With this chip set, we have demonstrated a transmission rate of 16 bits in parallel at 75 MHz, or with encoding overhead, a serial rate of 1.5 Gbit/s.

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