HP Labs Technical Reports



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Parallelization of Loops with Exits on Pipelined Architectures

Tirumalai, Partha P.; Lee, Meng; Schlansker, Michael S.

HPL-90-107

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Abstract: Modulo scheduling theory can be applied successfully to overlap Fortran DO loops on pipelined computers issuing multiple operations per cycle both with and without special loop architectural support [1, 2, 3]. This paper shows that a broader class of loops - repeat-until, while, and loops with more than one exit - where the trip count is not known beforehand, can also be overlapped efficiently on multiple issue pipelined machines. Special features that are required in the architecture, as well as compiler representations for accelerating these loop constructs, are discussed. Performance results are presented for a few select examples. A prototype scheduler is currently under construction at HP Laboratories.

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