HP Labs Technical Reports



High-Level Delay Estimation for Technology- Independent Logic Equations

Wallace, David E.; Chandrasekhar, Mandalagiri S.

HPL-90-150

Keyword(s):

Abstract: In this paper, we present a simple model for estimation the delay of a multi-level combinational logic description prior to a technology-dependent mapping phase. The model proposes that delay through a node varies logarithmically with both the complexity and the fan-out of the node's logic equation. This is a consequence of the observation that in high performance circuits, both the fan-in and fan-out of cells are bounded by by small numbers. We derive model parameters for three different industrial designs in each library. This model can serve as a proxy for delay during technology-independent logic optimization, much as literal counts serve as proxies for area.

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