HP Labs Technical Reports
Click here for full text:
I-Sim: An Instruction Cache Simulator
Tanquay, Donald O.
Abstract: As clock rates and instruction-level parallelism use increase, cache/memory systems will have difficulty efficiently handling the access demands for data and instructions. To gain some insight into the potential performance bottleneck of an overworked instruction cache, a fully parameterized instruction cache simulator has been created. This paper describes the simulator's modeling, implementation, and usefulness.
Back to Index