HP Labs Technical Reports

I-Sim: An Instruction Cache Simulator

Tanquay, Donald O.

HPL-92-11

Keyword(s):

Abstract: As clock rates and instruction-level parallelism use increase, cache/memory systems will have difficulty efficiently handling the access demands for data and instructions. To gain some insight into the potential performance bottleneck of an overworked instruction cache, a fully parameterized instruction cache simulator has been created. This paper describes the simulator's modeling, implementation, and usefulness.

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