HP Labs Technical Reports

Data Merging for Shared Memory Multiprocessors

Karp, Alan H.; Sakar, Vivek

HPL-92-138

Keyword(s):

Abstract: We describe an efficient software cache consistency mechanism for shared memory multiprocessors that supports multiple writers and works for cache lines of any size. Our mechanism relies on the fact that, for a correct program, only the global memory needs a consistent view of the shared data between synchronization points. Our delayed consistency mechanism allows arbitrary use of data blocks between synchronizations. pp In contrast to other mechanisms, our mechanism needs no modification to the processor hardware or any assistance from the programmer or compiler; the processors can use normal cache management policies. Since no special action is needed to use the shared data, the processors are free to act almost as if they are all running out of a single cache. The global memory units are nearly identical to those on currently available machines. We need to add only a small amount of hardware and/or software to implement our mechanism. The mechanism can even be implemented using network connected workstations.

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