HP Labs Technical Reports



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Instruction Level Parallel Processing

Fisher, Joseph A.; Rau, B. Ramakrishna.

HPL-92-2

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Abstract: The performance of microprocessors has increased steadily over the past twenty years at a rate of about 50% per year. This is the cumulative result of architectural improvements as well as increases in circuit speed. Moreover, this improvement has been obtained in a transparent, fashion, that is without requiring programmers to rethink their algorithms and programs, thereby enabling the tremendous proliferation of computers that we see today. To continue this performance growth, microprocessor designers have incorporated Instruction-level Parallelism (ILP) into new designs. ILP utilizes the parallel execution of the lowest level computer operations--adds, multiplies, loads, and so on--to increase performance transparently. The use of ILP promises to make possible, within the next few years, a CRAY-IS. This report provides an overview of ILP, with an emphasis on ILP architectures--superscalar, VLIW and dataflow processors--and the compiler techniques necessary to make ILP work well.

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