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Code Generation Schema for Modulo Scheduled DO-Loops and WHILE-Loops

Rau, B. Ramakrishna.; Schlansker, Michael S.; Tirumalai, Partha P.

HPL-92-47

Keyword(s):

Abstract: Software pipelining is an important instruction scheduling technique for efficiently overlapping successive iterations of loops and executing them in parallel. Modulo scheduling is one approach for generating such schedules. This paper addresses an issue which has received little attention thus far, but which is non-trivial in its complexity: the task of generating correct, high-performance code once the modulo schedule has been generated, taking into account the nature of the loop that is being scheduled. This issue is studied both with and without hardware features that are specifically aimed at supporting modulo scheduling.

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