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Achieving High Levels of Instruction-Level Parallelism with Reduced Hardware Complexity

Schlansker, Michael S.; Rau, B. Ramakrishna; Mahlke, Scott; Kathail, Vinod; Johnson, Richard; Anik, Sadun; Abraham, Santosh G.

HPL-96-120

Keyword(s): instruction-level parallelism; VLIW processors; superscalar processors; overlapped execution; out-of-order execution, overlapped execution; branch prediction; instruction scheduling; compile-time speculation; predicated execution; data speculation; HPL PlayDoh

Abstract: Instruction-level parallel processing (ILP) has established itself as the only viable approach for achieving the goal of providing continuously increasing performance without having to fundamentally re-write the application. ILP processors differ in their strategies for deciding exactly when, and on which functional unit, an operation should be executed. The alternatives lie somewhere on a spectrum depending on the extent to which these decisions are made by the compiler rather than by the hardware and on the manner in which information regarding parallelism is communicated by the compiler to the hardware via the program. HPL PlayDoh is a research architecture that has been defined to support research in ILP, with a bias towards VLIW processing. The overall objective of this research effort is to develop a suite of architectural features and compiler techniques that will enable a second-generation of VLIW processors to achieve high levels of ILP, across both scientific and non-scientific computations, but with hardware that is simple compared to out-of-order superscalar processors. The basic approach is to provide the program (compiler) more control over capabilities that, in superscalar processors, are typically microarchitectural (i.e., controlled by the hardware) by raising them to the architectural level.

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