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Indexing Memory Banks to Maximize Page Mode Hit Percentage and Minimize Memory Latency
Keyword(s): memory controller, page mode, indexing, addressing, performance, prefetching
Abstract: Many memory controllers today take the page mode gamble--they leave DRAM pages open on the chance that the next access will be on that same page. If it is, a row access delay is saved; if it is not, a row precharge delay may be incurred. Most studies have concentrated on whether this gamble is worthwhile, and how much it saves if it is. This report instead concentrates on how to organize your memory system so that the gamble succeeds as often as possible. Indeed, on sample traces, we show that the techniques originated here increase the page mode hit rate significantly; for a typical memory system organization and a small set of traces, the page mode hit rate increased from an average of 49% to an average of 87%. We also present results showing that inexpensive memory-side prefetching can further reduce the latency of memory reads--in our tests, half of the read data can be on the way to the bus drivers before the read is issued by the processor.
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