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In This Issue - February 1996 Volume 47 Issue 1

CURRENT ISSUE - February 1996 Volume 47 Issue 1 Symmetric multiprocessing means that a system can distribute its workload evenly over multiple CPUs. Thus, coupled with high-performance memory and I/O subsystems, a symmetric multiprocessing system is able to provide balanced high performance. Article 1 begins a group of articles that describe a new family of symmetric multiprocessing workstations and servers that have both low cost and high performance and satisfy a wide range of customer needs. First, there are the HP 9000 J-class high-end workstations and the HP 9000 K-class servers, which run the HP-UX* operating system, and then there are the HP 3000 Series 9x9KS servers, which run the MPE/iX operating system. The J-class workstation provides up to two-way symmetric multiprocessing, and the K-class server provides up to four-way symmetric multiprocessing. These systems are based on the superscalar PA-RISC processor called the PA 7200 (Article 3) and a high-speed memory bus called the Runway bus (Article 2).

The Runway bus, which is the backbone of these J/K-class platforms, is a new processor-to-memory-and-I/O interconnect that is ideally suited for for one-way to four-way symmetric multiprocessing for high-end workstations and midrange servers. The bus includes a synchronous, 64-bit, split-transaction, time multiplexed address and data bus that is capable of sustained memory bandwidths of up to 768 Mbytes per second in a four-way system.

One of the design goals for the Runway bus was to support the PA 7200 and future processors. The PA 7200 is an evolution of the high-performance, single-chip superscalar PA 7100 CPU design. The processor and the Runway bus are designed for a bus frequency of 120 MHz in a four-way multiprocessor system, which enables the sustained memory bandwidth of 768 Mbytes per second mentioned above. The PA 7200 contains all the circuits required for one processor in a multiprocessor system except for external cache arrays. Among some of the features contained in the PA 7200 are a new data cache organization, a prefetching mechanism, and two integer ALUs for general integer superscalar execution. The PA 7200 is described in Article 3 .

The increased functionality and higher operating frequency of today's VLSI chips have created a corresponding increase in the complexity of the verification process. In fact, chip verification activities now consume more time and resources than design. Article 4 describes the functional and electrical verification process used for the PA 7200 processor to ensure its quality and correctness. Since the design of the PA 7200 was based on the PA 7100 processor, verification could begin very early in the design because the same modeling language and simulator used for the PA 7100 could be used for the PA 7200. The article also describes debugging activities performed and the testability features provided on the PA 7200.

After investigating ways to improve customer application performance by observing existing platforms, the HP 9000 J/K-class design team determined that memory capacity, memory bandwidth, memory latency, and system-level parallelism (multiple CPUs and I/O devices all accessing memory in parallel) were key elements in achieving high performance. As Article 5 describes, a major improvement in memory bandwidth was achieved through system-level parallelism and memory interleaving, which were designed into the Runway bus and the J/K-class memory subsystem.

Cache coherency refers to the consistency of data between processors (and associated caches), memory modules, and I/O devices. For the HP 9000 J/K-class systems, a scheme called hardware cache coherent I/O was introduced. This technique involves the I/O system hardware in ensuring cache coherency, thereby reducing memory and processor overhead and contributing to greater system performance. Cache coherent I/O is discussed in Article 6.

Article 7 and Article 8 are more papers from the proceedings of HP's 1995 Design Technology Conference (DTC). The first article describes a 1.0625-Gbit/s Fibre Channel transmitter and receiver chipset. About three years ago HP introduced the first commercially available, two-chip, 1.4-gigabit-per-second, low-cost, serial data link interface, the HP HDMP G-link chipset. The new chipset, the HP HDMP-1512 (transmitter) and the HP HDMP-1514 (receiver) are a low-cost gigabit solution for Fibre Channel applications. The chipset implements the Fibre Channel FC-0 physical layer specification at 1.0625 Gbits/s. The transmitter features 20:1 data multiplexing with a comma character generator and a clock synthesis phase-locked loop, and includes a laser driver and a fault monitor for safety. The receiver performs clock recovery, 1:20 data demultiplexing, comma character detection, word alignment, and redundant loss-of-signal alarms for eye safety.

Article 8 discusses using the traditional software code inspection process for inspecting hardware descriptions written in Verilog HDL (hardware description language). The code inspection process for software development has been around for awhile and has proven itself to be an effective tool for finding design and code defects and sharing best practices among software engineers. The authors found that except for some issues specific to HDL, the format and results of their inspection process were very similar to the standard software inspection process.

The Telecommunications Industry Association (TIA) has released two standards (IS-95 and IS-97) that specify the various measurements required to ensure the compatibility of North American CDMA (code division multiple access) cellular transmitters and receivers. CDMA, which is used by the cellular telephone industry, is a class of modulation that uses specialized codes to provide multiple communication channels in a designated segment of the electromagnetic spectrum. Article 9 provides a tutorial overview of the operation of the algorithms in the HP 83203B CDMA cellular adapter, which is designed to make the base station measurements specified in the TIA standards. The article also covers the general concepts of CDMA signals and measurement and some typical measurements made with the HP 83203B.

C.L. Leath
Managing Editor

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