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April 1997, Article 17

April 1997, Article 17

Fast Turnaround of a Structured Custom IC Design Using Advanced Design Tools and Methodology

Through the use of several new tools and methodologies, a small team of engineers was able to design and verify a 1.7-million-FET chip in eight months. The tools and methodologies used included a set of guidelines and timing constraints that were met by the customer, a data path compiler, a highly tuned custom multiplier cell that was used in 87 locations, and an automated top-level power connection scheme.

by Rory L. Fisher, Stephen R. Herbener, John R. Morgan, and John R. Pessetto

Article 17 - apr97a17.pdf

This article is available in Adobe Acrobat format (PDF). To view this article you need to have Acrobat Reader 2.0 or later installed on your system. The Acrobat reader is available free of charge in Unix, Dos, Windows and Macintosh formats. You can download the reader from Adobe Systems (www.adobe.com)
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