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August 1997, Article 3

August 1997, Article 3

Functional Verification of the HP PA 8000 Processor

The advanced microarchitecture of the HP PA 8000 CPU has many features that presented significant new verification challenges. These include out-of-order instruction execution, register renaming, speculative execution, four-way superscalar operation, decoupled instruction fetch, concurrent system bus interface, and PA-RISC 2.0 architecture enhancements. Enhanced functional verification tools and processes were required to address this microarchitectural complexity.

by Steven T. Mangelsdorf, Raymond P. Gratias, Richard M. Blumberg, and Rohit Bhatia

Article 3 - aug97a3.pdf

This article is available in Adobe Acrobat format (PDF). To view this article you need to have Acrobat Reader 2.0 or later installed on your system. The Acrobat reader is available free of charge in Unix, Dos, Windows and Macintosh formats. You can download the reader from Adobe Systems (www.adobe.com)
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