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December 1997, Article 11

December 1997, Article 11

A 2.488-Gbit/s Silicon Bipolar Clock and Data Recovery Circuit for SONET Fiber-Optic Communications Networks

Adjustment-free clock and data recovery for 2.488-Gbit/s SONET applications is provided by a 1.77W, 3.45 X 3.45-mm2 chip implemented in a 25-GHz fT silicon bipolar process. The chip has an on-chip VCO and operates from 2 to 3 Gbits/s over process, voltage, and temperature variations with a single off-chip filter capacitor. For network monitoring, a highly reliable loss-of-signal detector is provided. For good mechanical, thermal, and RF performance, a custom package was developed using HP’s fine-line hybrid process.

by Richard Walker, Cheryl Stout, Chu-Sun Yen, and Lewis R. Dove

Article 11 - dec97a11.pdf

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