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foreword - Volume 4 Number 3

CURRENT ISSUE - Volume 4 Number 3 Robert M. Supnik,
Corporate Consultant, Vice President,
Technical Director, Alpha AXP and VAX Systems

If, as the popular saying goes, "Once is happenstance, twice is coincidence, three times is concerted action," then four consecutive instances of outstanding engineering achievement must be even more significant.

Since 1985, Digital has designed, developed, and shipped four generations of leadership VAX microprocessors and CMOS-based systems:

  • In 1985, the MicroVAX chip and resulting systems (such as the MicroVAX II and the VAXstation 2000)
  • In 1987, the CVAX chip and resulting systems (such as the MicroVAX 3800, the VAX 6000-200, and the VAXstation 3100)
  • In 1989, the Rigel chip and resulting systems (such as the VAX 4000-300, the VAX 6000-400, and the VAXstation 4000-60)
  • In 1991, the NVAX chip and resulting systems (such as the VAX 4000-500, the VAX 6000-600, and the VAXstation 4000-90)

The first three were described in the Digital Technical Journal issues of March 1986, August 1988, and Spring 1990, respectively; the last is the subject of this issue.

NVAX and its systems are the culmination of everything Digital and its engineers have learned about chip and system design over the last decade. The teams involved drew on many disciplines of hardware engineering, from microarchitecture to whole-system verification, to produce products of unparalleled performance and quality. The results speak for themselves.

  • From its initial shipment in October 1991 through today (a year later), NVAX was (and is) the fastest shipping CISC microprocessor in the world, whether measured by clock rate, SPECmarks, or transactions per second.
  • NVAX had fewer bugs after design completion, and went from tape-out to production more quickly than any microprocessor in Digital's history.
  • NVAX systems, spanning the range from workstation through mainframe, all shipped on or ahead of schedule, meeting or exceeding predicted performance.

An outstanding engineering achievement indeed!

The roots of NVAX can be traced back a decade to two distinct engineering programs: the High-end Systems Group's studies and implementations of highly pipelined VAX systems; and the Semiconductor Operations Group's projects in process development and microprocessor design.

The High-end Systems Group started work on highly parallel VAX systems in 1979, designing and building the VAX 8600 - the first VAX to include overlapped operand decoding (see the Digital Technical Journal, August 1985). At the same time, a research team described HyperVAX, a hypothetical fully pipelined design. Although HyperVAX was never built, its microarchitecture had a strong influence on the design of the VAX 9000, Digital's ECL mainframe (see the Digital Technical Journal, Fall 1990). And the microarchitecture of the VAX 9000, in turn, was the basis for NVAX.

The Semiconductor Operations Group also started work in 1979, formulating a multiyear program for the development of both semiconductor process technology and leading-edge microprocessors. This program spanned the years 1983 to 1987 and encompassed the development of the V-11, MicroVAX II, and CVAX microprocessors. In 1986, the plan was extended through 1991, encompassing the development of Rigel, Mariah (a Rigel variant), and a fourth-generation VLSI VAX code-named NVAX.

The goals for NVAX were ambitious. First, its targeted performance was more than 25 times faster than the VAX-11/780 (more than 10 times faster than the just-introduced CVAX chip), requiring significant improvements in both microarchitectural efficiency and in cycle time. Second, the chip development schedule coincided with the semiconductor process development schedule, requiring breakthroughs in concurrent development of product and process. And third, the time allotted from chip design completion to system shipment was the shortest in Digital's history, requiring unprecedented accuracy in chip and system design and verification.

As in past projects, work in various disciplines - semiconductor process development, chip microarchitecture and circuit design, microprocessor design tools, chip and system verification tools, and system design - cascaded from process through systems. First to start was a team from Advanced Semiconductor Development (ASD), which designed, simulated, and introduced into manufacturing CMOS-4, Digital's fourth generation of CMOS technology (see the Digital Technical Journal, Spring 1992). Building on prior technology generations, CMOS-4 contained many features - three layers of metal interconnect, salicide, precision resistors, local interconnect, deep diffusion ring - which directly supported the performance requirements of NVAX. In addition, ASD and Semiconductor Manufacturing pioneered new techniques for process transfer and qualification which dramatically shortened the time required to debug and qualify the CMOS-4 process.

In parallel, a design team from the Semiconductor Engineering Microprocessor Group initiated microarchitectural and circuit studies. The team started with the VAX 9000, but they quickly discovered that the difference in implementation media (multichip ECL gate arrays for the VAX 9000, single-chip custom CMOS for NVAX) required significant changes and new concepts. The microarchitecture sub-team used abstract and detailed performance models, studies from existing VAX systems, and experience with past designs to drive quantitative decisions about features and functions in NVAX. At the same time, the circuit sub-team formulated the overall design, circuit, and clocking methodologies for the chip and established the feasibility of the target cycle time, chip size, and layout floor plan.

As the microarchitectural concepts solidified, the design team realized that NVAX would be the largest and most complex chip ever designed at Digital, and that it would place unprecedented stress on the capabilities of both designers and design tools. Accordingly, they initiated a partnership with the Semiconductor Engineering CAD Group to improve current tools and to develop new tools. In addition to traditional areas like simulation, CAD development focused on improvements to productivity and accuracy through design synthesis, electromigration analysis, and capacitance and resistance extraction.

The size and complexity of the design, as well as the stringent schedule constraints, also dictated an early start on verification issues. The verification strategy formed an integral part of the design effort from the outset. The verification team developed tools and strategies for verifying the microarchitecture, the microcode, the logic, the circuits, the chip as a component, and the chip in a system.

Lastly, the various system groups - data center systems, office systems, workstations - began designing systems to utilize the NVAX chip's capabilities. Each group was able to build on the work done in past VAX systems and designed an NVAX-based system that functioned both as an upgrade of past systems and as a formidably competitive new system in its own right.

The work of these project teams dovetailed perfectly. NVAX completed design and taped-out in late November 1990, just as the CMOS-4 process was ready for chip prototyping. Due to the outstanding work of the chip design, system design, CAD, and verification teams, first-pass parts booted the VMS operating system at speed in early March 1991. The process team qualified CMOS-4 in October 1991, and systems using second-pass parts shipped for revenue that same month - three months ahead of schedule - with performance significantly greater than the original goal.

Clearly, the outstanding results from all the NVAX engineering projects are neither happenstance nor coincidence; rather, they represent concerted action - team excellence and individual brilliance - at its finest. Hundreds of people contributed to the outcome. This issue of the Digital Technical Journal is their story.

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