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Performance Emulators for "The Machine": NVM and Interconnect

Performance Emulator for NVM
The next generation of HP hardware The Machine will be based on new non-volatile memory (NVM) technologies, such as memristors. This can radically change system and software design, and enable new style of Big Data processing applications. However, the commercial unavailability of new NVMs technologies and uncertainty of their performance characteristics make it difficult to assess new system software stacks and to study their performance impact on future workloads. To bridge this gap and encourage an early design phase, we are building a DRAM-based performance emulation platform, that leverages features available in commodity hardware, to emulate different latency and bandwidth characteristics of future NVM technologies. We evaluate the accuracy and effectiveness of our emulator by executing a set of specially designed memory-intensive applications and benchmarks on a multi-socket machine with a range of memory latencies. The designed emulator enables an efficient emulation of a wide range of NVM latencies and bandwidth characteristics for performance evaluation of emerging byte-addressable NVMs and their impact on applications performance without modifying or instrumenting their source code.

Interconnect Emulator: InterSense
Many modern large graph and Big Data processing applications operate on datasets that do not fit into DRAM of a single machine. This leads to a design of scale-out applications, where the application dataset is partitioned and processed by a cluster of machines. Distributed memory applications exhibit complex behavior: they tend to interleave computations and communications, use bursty transfers, and utilize global synchronization primitives. This makes it difficult to analyze the communication layer impact on the application performance and answer the questions: how interconnect latency or bandwidth characteristics may change the application performance? will the application performance scale when processed by a larger-scale system? The next generation of HP hardware The Machine will employ a new style photonic interconnect that will have radically different system performance characteristics. In this work, we introduce a novel emulation framework, called InterSense, which is implemented on top of existing high-speed interconnect, such as InfiniBand, and which offers two performance knobs for changing the (today's) interconnect bandwidth and latency. InterSense supports an efficient emulation of a wide range of interconnect latencies and bandwidth characteristics for enabling performance and scalability analysis of Big Data applications.

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