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An integrated power, area, and timing modeling framework for multicore and manycore architectures
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McPAT (Multicore Power, Area, and Timing) is an integrated power, area, and timing modeling framework for multithreaded, multicore, and manycore architectures. It models power, area, and timing simultaneously and consistently and supports comprehensive early stage design space exploration for multicore and manycore processor configurations ranging from 90nm to 22nm and beyond. McPAT includes models for the components of a complete chip multiprocessor, including in-order and out-of-order processor cores, networks-on-chip, shared caches, and integrated memory controllers. McPAT models timing, area, and dynamic, short-circuit, and leakage power for each of the device types forecast in the ITRS roadmap including bulk CMOS, SOI, and double-gate transistors. McPAT has a flexible XML interface to facilitate its use with different performance simulators.

The paper in MICRO'09 introduces McPAT and showcases its capabilities, with the authors' copy available at MICRO'09_McPAT. A technical report on McPAT is available at McPAT technical report. McPAT Beta source code can be obtained by downloading the gzip'ed tar files of McPAT 0.8 , extracting the file (tar -xzvf mcpat*.tar.gz), and running make. The McPAT 1.0 release (the latest release) is available at https://code.google.com/p/mcpat/

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