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EPIC: An Architecture for Instruction-Level Parallel Processors

Schlansker, Michael; Rau, B. Ramakrishna


Keyword(s): EPIC architecture; VLIW architecture; instruction- level parallelism; MultiOp; non-unit assumed latencies; NUAL; rotating register files; unbundled branches; control speculation; speculative opcodes; exception tag; predicated execution; fully-resolved predicates; wired-OR and wired-AND compare opcodes; prioritized loads and stores; data speculation; cache specifiers; precise interrupts, NUAL-FREEZE AND nual- drain semantics; delay buffers; replay buffers; EQ and LEQ semantics; latency stalling; MultiOp-P and MultiOp-S semantics; dynamic translation; MultiTemplate and VariOp instruction formats; history of EPIC

Abstract: Over the past two and a half decades, the computer industry has grown accustomed to, and has come to take for granted, the spectacular rate of increase of microprocessor performance, all of this without requiring a fundamental rewriting of the program in a parallel form, without using a different algorithm or language, and often without even recompiling the program. The continuation of this trend is the topic of discussion of this report. For the time being at least, instruction-level parallel processing has established itself as the only viable approach for achieving the goal of providing continuously increasing performance without having to fundamentally re-write applications. In this report, we introduce the Explicitly Parallel Instruction Computing (EPIC) style of architecture which was developed, starting eleven years ago, to enable higher levels of instruction-level parallelism without unacceptable hardware complexity. We explain the philosophy underlying EPIC as well as the challenges faced as a result of adopting this philosophy. We also describe and discuss the set of architectural features that together characterize the EPIC style of architecture, and which can be selectively included in some specific instance of an EPIC instruction set architecture.

80 Pages

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