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Verification of a Synthesisable Reed-Solomon ECC Core

Banks, David

HPL-2001-125

Keyword(s): Reed-Solomon; error correction; verilog; synthesis; synthesisable; hardware; ECC; Galois field

Abstract: In this report we describe the verification of a Reed-Solomon error correction core that supports errors and erasures decoding. In a second report HPL-2001-124 we describe the design of this core. The verification was performed using both simulation and prototyping. The simulation environment consisted of automatic test vector (codeword) generation for a variety of tests, unit delay simulation of a gate-level netlist in Verilog-XL, and comparison of the simulation results against an independently developed Reed-Solomon ECC model written in C. The prototyping environment consisted of a Xilinx FPGA containing the ECC block with a flexible pattern generator, together with circuitry for adding errors and erasures, and circuitry for accumulating test results. Tests were configured using a C program (running under Linux), which communicated with the hardware under test using a standard parallel port interface. Overall, we ran 1,147,000 vectors through the simulation, and 10,176,000,000 random vectors through the prototype. No failures were detected.

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