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Scalable Networking for Next-Generation Computing Platforms

Turner, Yoshio; Brecht, Tim; Regnier, Greg; Saletore, Vikram; Janakiraman, G. (John); Lynn, Brian

HPL-2004-13

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Abstract: We propose a technology strategy for enabling applications to scale to next-generation levels of I/0 scalability and communication performance on industry standard platforms. The strategy combines efficient packet processing and scalable I/0 concurrency, potentially enabling Ethernet and TCP to approach the latency and throughput performance offered by today's System Area Networks. We target the performance of communication-centric applications, initially using a web server as the application for concept validation. Our approach integrates two components to provide a complete networking stack for user-level applications. The first component is the ETA architecture developed at Intel Labs, where one or more server processor cores are dedicated for network packet processing. This architecture reduces processing overhead by avoiding costly interrupts and context switches, and by exposing VIA-style user-level communication primitives which reduce data copies and bypass the operating system for most I/0 operations. The second component is an asynchronous I/0 (AI0) programming model, which allows a single thread to issue I/0 operations without being blocked and to receive asynchronous events that signify the completion of previously issued I/0 operations. The AI0 programming model allows applications to achieve scalable concurrency without the overhead of software threads. This paper will describe the components of our proposed networking stack, a web server application designed to take advantage of this networking stack, and our plans to evaluate the performance benefits of this approach. Notes: Copyright IEEE. To be published in and presented at the Third Annual Workshop on System Area Network (SAN-3) held in conjunction with HPCA-10, 14 February 2004, Madrid, Spain

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