HP Labs Technical Reports
Click here for full text:
Mach on a Virtually Addressed Cache Architecture
Chao, Chia; Mackey, Milon; Sears, Bart
Abstract: Mach shares memory between tasks by virtual address aliasing. This means a physical page can be mapped to more than one virtual page at a time. This works well on hardware architectures that use a physically addressed cache, but can cause some problems for architectures that use a virtually addressed cache, resulting in less than best possible performance. This memo describes four experiments that were tried to improve the performance of Mach running on a machine with a virtually addressed cache. The experiments were implemented and measured against a collection of benchmarks. The measurements were then compared to those taken on a "base" implementation of Mach on the same hardware to get a clear idea of the performance benefit of each experiment.
Back to Index